Interrupt model and processor availability

This chapter documents the SoftDevice interrupt model, how interrupts are forwarded to the application, and describes how long the processor is used by the SoftDevice in different priority levels.

Exception model
As the SoftDevice, including the MBR, needs to handle some interrupts, all interrupts are routed through the MBR and SoftDevice. The ones that should be handled by the application are forwarded and the rest are handled within the SoftDevice itself. This section describes the interrupt forwarding mechanism.
Interrupt priority levels
This section gives an overview of interrupt levels used by the SoftDevice and the interrupt levels that are available for the application.
Processor usage patterns and availability
This section gives an overview of the processor usage patterns for features of the SoftDevice and the processor availability to the application in stated scenarios.