This section describes nRF7001 hardware and layout specifications.

Pin assignments

The pin assignment figure and tables describe the pinouts for the device. There are also recommendations for how the General-Purpose Input/Output (GPIO) pins should be configured, in addition to any usage restrictions.

Figure 1. Pin assignments
Pin assignments
Table 1. Pin assignments
Pin Name Function Description
1 OTPVDD Power
2 N.C. Do not connect
3 N.C. Do not connect
4 N.C. Do not connect
5 N.C. Do not connect
6 N.C. Do not connect
7 N.C Do not connect
8 VSS Power
9 TXRF<0> RF 2.4 GHz
10 PAVDD<0> Power
11 SXLDO Power
12 PALDO Power
13 VBAT Power
14 RFVDD Power
15 RFBUCKVDD Power
16 XOLDO Power
17 XOP Analog input 40 MHz crystal (or TCXO output if using an external TCXO)
18 XON Analog input 40 MHz crystal (or N.C. if using an external TCXO)
19 AFELDO Power
20 AFEVBAT Power
21 N.C. Do not connect
22 N.C. Do not connect
23 N.C. Do not connect
24 N.C. Do not connect
25 BUCKVBAT Power
26 BUCKOUT Power DCDC output
27 BUCKVSS Power DCDC GND
28 BUCKVSS Power DCDC GND
29 BUCKVMID Power Voltage reference decoupling pin
30 BUCKEN Digital I/O PWR IP enable pin
31 BUCKVBATS Power
32 PWRBUCKVDD Power
33 DIGVDD Power
34 PWRIOVDD Power
35 QSPI_CLK

SPI_CLK

 Digital I/O QSPI Clock

SPI Clock
36 QSPI_SS

SPI_SS

 Digital I/O QSPI Slave select

SPI Slave select
37 QSPI_DATA0

SPI_MOSI

 Digital I/O QSPI data

SPI data
38 QSPI_DATA1

SPI_MISO

 Digital I/O QSPI data

SPI data
39 QSPI_DATA2 Digital I/O QSPI data
40 QSPI_DATA3 Digital I/O QSPI data
41 COEX_STATUS0 Digital I/O Coex interface
42 COEX_REQ Digital I/O Coex interface
43 COEX_GRANT Digital I/O Coex interface
44 SW_CTRL0 Digital I/O External switch control
45 SW_CTRL1 Digital I/O External switch control
46 HOST_IRQ Digital I/O Host processor interrupt request
47 VSS Power
48 IOVDD Power
49 (Die pad) VSS Power Ground pad. Exposed die pad must be connected to ground (VSS) for proper device operation.

Mechanical specifications

Dimensions in millimeters for the QFN 6 x 6 mm package.

Table 2. Package dimensions in millimeters
A A1 A2 b D E D2 E2 e K L
Min. 0.8 0.15 5.9 5.9 0.2 0.35
Nom. 0.85 0.035 0.65 0.2 6 6 4.6 4.6 0.4 0.4
Max. 0.9 0.05 0.25 6.1 6.1 0.45

Reference circuitry

To ensure good RF performance when designing Printed Circuit Board (PCB)s, it is highly recommended to use the PCB layouts and component values provided by Nordic Semiconductor.

Reference schematic

Circuit configuration, showing the schematic and Bill of Materials (BOM) table for nRF7001.

Figure 2. nRF7001 reference schematic
image/svg+xml I R Q S W _ C T R L 1 S W _ C T R L 0 C O E X _ G R A N T C O E X _ S T A T U S C O E X _ R E Q Q S P I _ D A T A 3 Q S P I _ D A T A 2 Q S P I _ D A T A 1 / S P I _ M I S O VDDIO Q S P I _ D A T A 0 / S P I _ M O S I Q S P I _ S S / S P I _ S S Q S P I _ C L K / S P I _ C L K OTPVDD 1 NC 2 NC 3 NC 4 NC 5 NC 6 NC 7 VSS 8 TXRF0 9 PAVDD0 10 SXLDO 11 PALDO 12 V B A T 1 3 R F V D D 1 4 R F B U C K V D D 1 5 X O L D O 1 6 X O P 1 7 X O N 1 8 A F E L D O 1 9 A F E V B A T 2 0 N C 2 1 N C 2 2 N C 2 3 N C 2 4 BUCKVBAT 25 BUCKOUT 26 BUCKVSS 27 BUCKVSS 28 BUCKVMID 29 BUCKEN 30 BUCKVBATS 31 PWRBUCKVDD 32 DIGVDD 33 PWRIOVDD 34 Q S P I _ C L K 3 5 Q S P I _ S S 3 6 Q S P I _ D A T A 0 3 7 Q S P I _ D A T A 1 3 8 Q S P I _ D A T A 2 3 9 Q S P I _ D A T A 3 4 0 C O E X _ R E Q 4 2 C O E X _ S T A T U S 0 4 1 C O E X _ G R A N T 4 3 S W _ C T R L 0 4 4 S W _ C T R L 1 4 5 H O S T _ I R Q 4 6 V S S 4 7 I O V D D 4 8 V S S 4 9 nRF7001 U1 nRF7001 QFAA PWRIOVDD PWRIOVDD A N T VBAT BUCK_EN SXLDO PALDO VBAT VDD_BUCK VBAT OUT 3 IN 1 GND 2 GND 4 F1 LP/BP Filter VDD_BUCK Connect to an isolated metal plane on top layer with vias to isolated metal plane on layer2 connecting only near thermal vias on the IC Paddle. See the layout in layer2. VBAT C18 2.2 µ F C17 100nF C11 4.7 µ F C14 0.47 µ F X1 40MHz C3 0.22 µ F C5 1.0 µ F C6 4.7 µ F C13 22nF C15 2.2 µ F C16 1.0 µ F C10 1.0 µ F C7 2.2 µ F C9 2.2 µ F L1 3.3 µ H C8 10nF C1 4.7 µ F C2 4.7 µ F C4 0.47 µ F C12 100nF
Table 3. BOM for nRF7001
Designator Value Description Note
U1 nRF7001 Wi-Fi® 6 companion chip
F1 LP_Filter 2.45 GHz Center Frequency Low Pass RF Filter, 100 MHz Bandwidth 0.5 dB
X1 40 MHz Crystal SMD 1612, 40 MHz, Cl=8 pF ESR max 100 Ω
L1 3.3 µH Inductor, 1 A, ±20%, 200 mΩ
C1, C2, C6, C11 4.7 µF Capacitor, Ceramic, 4.7 µF 25 V X6S 0603, ±10%

Place C1 close to BUCKVBAT pin

Place C2 close to L1

Place C11 close to PALDO pin
C3 0.22 uF Capacitor, Ceramic, 0.22 µF 10 V X5R 0201, ±10%

Place C3 close to RFBUCKVDD pin
C4, C14 0.47 uF Capacitor, Ceramic, 0.47 µF 6.3 V X5R 0201, ±10%

Place C4 close to PWRBUCKVDD pin
C5 1.0 µF Capacitor, Ceramic, 1.0 µF 35 V X5R 0402, ±10%
C7, C18 2.2 µF Capacitor, Ceramic, 2.2 µF 16 V X7S 0603, ±10%

Place C7 close to BUCKVBATS pin
C8 10 nF Capacitor, Ceramic, 10 nF 16 V X7R 0201, ±10%
C9 2.2 µF Capacitor, Ceramic, 2.2 µF 25 V X5R 0402, ±10%
C10 1.0 µF Capacitor, Ceramic, 1.0 µF 16 V X6S 0402, ±10%
C12 100 nF Capacitor, Ceramic, 100 nF 16 V X7S 0201, ±10%

Place C12 close to PAVDD0 pin
C13 22 nF Capacitor, Ceramic, 22 nF 10 V X5R 0201, ±10%
C15 2.2 µF Capacitor, Ceramic, 2.2 µF 10 V X5R 0201, ±10%
C16 1.0 µF Capacitor, Ceramic, 1.0 µF 10 V X7S 0402, ±10%
C17 100 nF Capacitor, Ceramic, 100 nF 16 V X7S 0201, ±10%

Supply sequencing requirements

The various supplies and BUCKEN need to be sequenced in order with delay requirements.

The power up sequence and requirements are:

  • Supply VBAT/BUCKVBAT/BUCKVBATS/AFEVBAT
  • Wait ≥ 6 ms
  • Assert BUCKEN
  • Wait ≥ 1 ms
  • Supply IOVDD

PWRIOVDD is an internally generated supply, used for supplying OTPVDD through an external connection. It cannot be used for anything else. This supply is automatically controlled in the device.

The power-down sequence and requirements are:

  • De-assert BUCKEN and power down IOVDD
  • Power down VBAT

There are no specific timing delay requirements as long as the sequence is correct.

Supply system alternatives

nRF7001 can be powered up/down from a host dynamically. This dynamic control uses the BUCKEN pin and an external switch to control the IOVDD supply. Both the BUCKEN pin and the external switch control are driven from a GPIO on the host, controlled by the Wi-Fi driver.

There are two options (high voltage and normal voltage) for connecting nRF7001 to an nRF5340 host, supporting dynamic powerup/powerdown of the nRF7001. This dynamic control utilises an external switch to control the IOVDD supply.

The following figure shows the recommended connection between nRF7001 and the host Microcontroller Unit (MCU) (nRF5340).

Figure 3. Supply system - high voltage mode
Supply system - high voltage mode

Both nRF5340 (used in high voltage mode) and nRF7001 can be supplied from a single 3.6 V supply.

nRF5340 can provide a 1.8 V supply used for the IO supply on nRF7001. An external switch is used to disconnect IOVDD on nRF7001 when not in use. The control of the switch is handled by the Wi-Fi driver on nRF5340.

Figure 4. Supply system - normal voltage mode
Supply system - normal voltage mode

QSPI/SPI connections

The nRF7001 can be connected to the nRF5340 host either with a Quad Serial Peripheral Interface (QSPI) or a Serial Peripheral Interface (SPI). QSPI is normally the preferred option, but in cases where QSPI on the host is used for other purposes SPI can be used.

The following figure shows the connection using QSPI between nRF7001 and the host MCU (nRF5340).

Figure 5. QSPI connection
Page-1 Sheet.94 Dynamic connector.93 Dynamic connector Sheet.86 Sheet.87 Sheet.90 32 MHz 32 MHz Sheet.118 Dynamic connector.93 Dynamic connector Sheet.121 Sheet.122 Sheet.123 40 MHz 40 MHz Dynamic connector Dynamic connector.126 Nordic Lake nRF5340 nRF5340 Sheet.103 SCK SCK Sheet.104 GPIO GPIO Sheet.105 GPIO GPIO Sheet.106 GPIO GPIO Nordic Lake.65 nRF7001 nRF7001 Sheet.110 HOST_IRQ HOST_IRQ Sheet.111 COEX COEX Sheet.112 BUCKEN BUCKEN Sheet.109 QSPI_CLK QSPI_CLK Dynamic connector.129 Dynamic connector.130 Sheet.159 Sheet.160 Sheet.161 Sheet.162 QSPI_SS QSPI_SS Sheet.163 QSPI_DATA0 QSPI_DATA0 Sheet.164 QSPI_DATA1 QSPI_DATA1 Sheet.165 QSPI_DATA2 QSPI_DATA2 Sheet.166 QSPI_DATA3 QSPI_DATA3 Sheet.167 CSN CSN Sheet.168 IO0 IO0 Sheet.169 IO1 IO1 Sheet.170 IO2 IO2 Sheet.171 IO3 IO3 Dynamic connector.172 Dynamic connector.173 Dynamic connector.174 Dynamic connector.175 Dynamic connector.176

The following figure shows the connections using SPI between nRF7001 and nRF5340.

Figure 6. SPI connection
Page-1 Dynamic connector.178 Sheet.94 Dynamic connector.93 Dynamic connector Sheet.86 Sheet.87 Sheet.90 32 MHz 32 MHz Sheet.118 Dynamic connector.93 Dynamic connector Sheet.121 Sheet.122 Sheet.123 40 MHz 40 MHz Dynamic connector Dynamic connector.126 Nordic Lake nRF5340 nRF5340 Sheet.103 SCK SCK Sheet.104 GPIO GPIO Sheet.105 GPIO GPIO Sheet.106 GPIO GPIO Nordic Lake.65 nRF7001 nRF7001 Sheet.110 HOST_IRQ HOST_IRQ Sheet.111 COEX COEX Sheet.112 BUCKEN BUCKEN Sheet.109 SPI_CLK SPI_CLK Dynamic connector.129 Dynamic connector.130 Sheet.159 Sheet.160 Sheet.161 Sheet.162 SPI_SS SPI_SS Sheet.163 SPI_MOSI SPI_MOSI Sheet.164 SPI_MISO SPI_MISO Sheet.167 CSN CSN Sheet.168 MOSI MOSI Sheet.169 MISO MISO Dynamic connector.172 Dynamic connector.173 Dynamic connector.174 Sheet.177 QSPI QSPI Sheet.182 Sheet.183

TCXO connection

It is possible to use an external TCXO instead of a crystal.

This option does not require production line trimming, but it will draw more current and hence significantly degrade sleep performance. The TCXO should be disabled when in Shutdown mode to reduce current consumption. It is not possible to dynamically control the TCXO when transitioning between Sleep and Active states. The TCXO should have a typical clipped sine wave output of 0.4 V peak (maximum 0.6 V peak) and be connected through a series capacitor (typically 10 nF).

PCB layout example

The PCB layout in this section is a reference layout for the QFN package.

It is highly recommended to use the layout example as presented with the following boundary clarifications:
  • Keep the antenna connection short.
  • Connect VBAT supply to component C6 in the bottom layer.
  • Connect IOVDD supply to component C18 in the bottom layer.
Figure 7. Top silk layer
Top silk layer
Figure 8. Top layer
Top layer
Figure 9. Mid layer 1
Mid layer 1
Figure 10. Mid layer 2
Mid layer 2
Figure 11. Bottom layer
Bottom layer