nRF52832 Revision 1 Errata

nRF52832 Revision 1 Errata
Revision history
New and inherited anomalies
[12] COMP: Reference ladder is not correctly calibrated
[15] POWER: RAM[x].POWERSET/CLR read as zero
[20] RTC: Register values are invalid
[31] CLOCK: Calibration values are not correctly loaded from FICR at reset
[36] CLOCK: Some registers are not reset when expected
[51] I2S: Aligned stereo slave mode does not work
[54] I2S: Wrong LRCK polarity in Aligned mode
[55] I2S: RXPTRUPD and TXPTRUPD events asserted after STOP
[58] SPIM: An additional byte is clocked out when RXD.MAXCNT = 1
[64] NFCT: Only full bytes can be received or transmitted, but supports 4-bit frame transmit
[66] TEMP: Linearity specification not met with default settings
[67] NFCT, PPI: Some events cannot be used with the PPI
[68] CLOCK: EVENTS_HFCLKSTARTED can be generated before HFCLK is stable
[72] NFCT, PPI: TASKS_ACTIVATE cannot be used with the PPI
[74] SAADC: Started events fires prematurely
[75] MWU: Increased current consumption
[76] LPCOMP: READY event is set sooner than it should
[77] CLOCK: RC oscillator is not calibrated when first started
[78] TIMER: High current consumption when using timer STOP task only
[79] NFCT: A false EVENTS_FIELDDETECTED event occurs after the field is lost
[81] GPIO: PIN_CNF is not retained when in debug interface mode
[83] TWIS: STOPPED event occurs twice if the STOP task is triggered during a transaction
[84] COMP: ISOURCE not functional
[86] SAADC: Triggering START task after offset calibration may write a sample to RAM
[87] CPU: Unexpected wake from System ON Idle when using FPU
[88] WDT: Increased current consumption when configured to pause in System ON idle
[89] GPIOTE: Static 400 µA current while using GPIOTE
[91] RADIO: Radio performance using CSP package version
[97] GPIOTE: High current consumption in System ON Idle mode
[101] CLOCK: Sleep current increases after soft reset
[102] RADIO: PAYLOAD/END events delayed or not triggered after ADDRESS
[106] RADIO: Higher CRC error rates for some access addresses
[107] RADIO: Immediate address match for access addresses containing MSBs 0x00
[108] RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode
[109] DMA: DMA access transfers might be corrupted
[113] COMP: Single-ended mode with external reference is not functional
[132] CLOCK: The LFRC oscillator might not start
[136] System: Bits in RESETREAS are set when they should not be
[138] RADIO: Spurious emission on GPIO exceeds limits in radiated tests
[141] NFCT: HFCLK not stopped when entering SENSE mode
[143] RADIO: False CRC failures on specific addresses
[146] CLOCK: LFRC frequency deviation
[149] TWIM: First clock pulse after clock stretching may be too long or too short
[150] SAADC: EVENT_STARTED does not fire
[155] GPIOTE: IN event may occur more than once on input edge
[156] GPIOTE: Some CLR tasks give unintentional behavior
[163] FICR: Code and RAM size fields do not match chip specification
[173] GPIO: Writes to LATCH register take several CPU cycles to take effect
[176] System: Flash erase through CTRL-AP fails due to watchdog time-out
[178] SAADC: END event firing too early
[179] RTC: COMPARE event is generated twice from a single RTC compare match
[181] NFCT: Invalid value in FICR for double-size NFCID1
[183] PWM: False SEQEND[0] and SEQEND[1] events
[192] CLOCK: LFRC frequency offset after calibration
[194] I2S: STOP task does not switch off all resources
[196] I2S: PSEL acquires GPIOs regardless of ENABLE
[201] CLOCK: EVENTS_HFCLKSTARTED might be generated twice
[204] RADIO: Switching between TX and RX causes unwanted emissions
[210] GPIO: Bits in GPIO LATCH register are incorrectly set to 1
[212] SAADC: Events are not generated when switching from scan mode to no-scan mode with burst enabled
[213] WDT: WDT configuration is cleared when entering system OFF
[218] NFCT: Frame delay timing is too short after SLP_REQ
[219] TWIM: I2C timing spec is violated at 400 kHz
[220] CPU: RAM is not ready when written
[241] SAADC: Static 400 µA current after SAADC is disabled
[245] RADIO: CRC is wrong when data whitening is enabled and address field is included in CRC calculation
[252] SAADC: Unexpected behavior when TASKS_CALIBRATEOFFSET is used during sampling
[262] POWER: CPU does not resume execution after CPU IDLE
[266] SAADC: Gain error exceeds specified value when using VDD as reference
[275] COMP: Static 300 µA current after COMP has been enabled
[276] SAADC: Static 400 µA current after SAADC is disabled in scan mode
[277] GPIO: Static current is 300 µA higher than expected with PIN_CFN:SENSE enabled

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