nRF5340 Engineering A Errata

nRF5340 Engineering A Errata
Change log
New and inherited anomalies
[1] REGULATORS: VREGH short circuit protection is not functional
[2] TAD: Accessing external QSPI memory without configuring QSPI makes application core unresponsive
[3] SAADC: VDDHDIV5 is not functional
[4] CLOCK: Changing application core frequency register HFCLKCTRL requires additional register initialization
[5] TAD: Trace is not functional when application core is running at 128 MHz
[6] NVMC: Disabling instruction cache causes skip of next instruction
[7] USBD: USBD is not functional
[8] WDT: WDT1 is not functional
[9] TAD: TPIU is missing from ROM table
[10] CCM: Reading CNFPTR, INPTR, OUTPTR, and SCRATCHPTR pointers returns incorrect address
[11] ACL: Reading ACL[n].ADDR returns incorrect address
[12] QSPI: SCKFREQ is not functional at 96 MHz
[13] GPIO: Bits in LATCH register are incorrectly set to 1
[14] TIMER: CC[6] and CC[7] are not functional
[15] UARTE: Odd parity setting is not functional
[16] RADIO: POWER register is not functional
[18] I2S: 32-bit sample widths and 8-bit sample in a 16-bit half-frame are not functional
[19] SPU: Flash memory space is divided into 32 regions of 32 KiB
[20] RTC: TASKS_CAPTURE[n], SUBSCRIBE_CAPTURE[n], and SHORTS registers are not functional
[21] TWIM: 1000 kbps baud rate is not functional
[22] SPU: CPULOCK register is not functional
[23] SAADC: Events are not generated when switching from scan mode to no-scan mode with BURST enabled
[26] CTRL-AP: APPROTECT.DISABLE and SECUREAPPROTECT.DISABLE registers are not functional
[27] CTRL-AP: STATUS register is not functional
[28] TIMER: INTEN register is not functional
[29] SWI: SWIRQ is not functional
[30] RESET: LCTRLAP field in RESETREAS register is not functional
[31] TAD: Multidrop serial wire debug is not functional
[32] GPIO: GPIO pins assigned to network core do not retain their state in System OFF mode
[33] CLOCK: LFRC frequency starts drifting even if calibration task is triggered
[34] CTRL-AP: Erase all is not functional with APPROTECT enabled
[36] I2S: Excessive power consumption after using I2S STOP task
[37] TWIM: First clock pulse after clock stretching may be too long or too short
[42] CLOCK: Reset value of HFCLKCTRL is invalid
[43] QSPI: Reading QSPI registers after XIP might halt application CPU
[44] UARTE: TASKS_RESUME impacts UARTE
[45] SPIM: Receive is not functional at 32 Mbps
[46] CLOCK: LFRC has higher current consumption
[47] TWIM: I2C timing spec is violated at 400 kHz
[49] POWER: SLEEPENTER and SLEEPEXIT events are asserted after pin reset
[50] SPU: Arm TrustZone region numbers for FICR, UICR, CACHEINFO, and CACHEDATA are incorrect
[51] SPU: Accessing FICR, UICR, CACHEINFO, or CACHEDATA from non-secure state gives bus error
[52] VMC: RAM block is not writable immediately on power-up
[53] REGULATORS: Current consumption in normal voltage mode is higher in System ON idle
[54] REGULATORS: Current consumption in normal voltage mode is higher in System ON idle and System OFF
[55] RESET: Bits in RESETREAS are set when they should not be
[57] I2S: EVENTS_FRAMESTART and PUBLISH_FRAMESTART registers are not functional
[58] I2S: BYPASS in CONFIG.CLKCONFIG is not functional
[59] QDEC: QDEC0 is not functional
[62] UICR: HFXOCNT register is not functional
[64] REGULATORS: VREGMAIN has invalid configuration when CPU is running
[65] SAADC: Events are not generated when switching from scan mode to no-scan mode with BURST disabled
[66] GPIO: P1.PIN_CNF[2-3], P0.PIN_CNF[8-18] DRIVE cannot be set in some configurations
[67] DEVICE: ESD HBM is less than 2 kV
[69] REGULATORS: VREGMAIN configuration is not retained in System OFF
[70] NFCT: Event FIELDDETECTED may be generated too early
[71] NFCT: Frame delay timing is too short after SLP_REQ
[72] REGULATORS: Current consumption in high voltage mode is higher in System ON idle and System OFF
[73] TIMER: ONESHOTEN[n] registers are located at an incorrect address offset
[74] TIMER: COMPARE[i]_STOP is located at an incorrect bit number in the SHORTS register
[75] PWM: False SEQEND[0] and SEQEND[1] events are generated
[76] DPPI: Non-secure code can detect secure events
[77] TAD: Debug power-up request is not acknowledged
[79] QDEC: QDEC1 is not functional
[80] PWM: PWM3 is not functional
[81] SPIM: SPIM2 and SPIM3 are not functional
[82] TWIM: TWIM2 and TWIM3 are not functional
[83] SPIS: SPIS2 and SPIS3 are not functional
[84] UARTE: UARTE2 and UARTE3 are not functional
[85] NVMC: Reading or executing from flash memory can lead to errors when scaling frequency
[86] CLOCK: EVENTS_DONE is not functional
[87] RADIO: RSSI parameter adjustment
[90] GPIO: PIN_CNF[n] MCUSEL is reset by application core soft reset
[91] RADIO: Ramp-up is slower than specified
[93] NVMC: Writing to flash requires high voltage on VREGRADIO
[95] REGULATORS: VREGRADIO DC/DC can malfunction
[97] UICR: ERASEPROTECT or APPROTECT is occasionally enabled or device startup may fail
[103] CPU: Network core executing code from application core flash causes bus fault
[105] SPIM, SPIS, TWIM, TWIS, UARTE: Peripheral has higher than expected current consumption
[106] SPIM: SPIM4 is not functional with GPIO.PIN_CNF[n].MCUSEL configured as Peripheral
[109] GPIOTE: LATENCY register is not functional
[110] QSPI: QSPI is not functional with GPIO.PIN_CNF[n].MCUSEL configured as Peripheral
[113] RADIO: Reading DTX in MODECNF0 gives incorrect value
[114] CPU: Accessing application core flash causes processor to become unresponsive
[115] CRYPTOCELL, USBD: Peripheral cannot do DMA transfers from flash when application core processor is sleeping
[116] RADIO: Device spurious emission during transmit is higher than expected

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