nRF9161 Revision 1 Errata

nRF9161 Revision 1 Errata
Revision history
New and inherited anomalies
[1] I2S: Excessive power consumption after using STOP task
[2] NVMC: CPU code execution from RAM halted during flash page erase operation
[4] GPIO: Bits in GPIO LATCH register are incorrectly set to 1
[6] POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset
[7] UICR: Wrong code memory Read or Write after accessing UICR
[9] SAADC: Reduced SFDR
[15] REGULATORS: Supply regulators default to LDO mode after reset
[21] NVMC: Disabling instruction cache causes skip of next instruction
[23] UART: TASKS_RESUME impacts UARTE
[24] NVMC: CPU is not halted for page erase in debug session
[26] CLOCK, LFXO: System locks up when set in System ON IDLE while waiting for EVENTS_LFCLKSTARTED
[28] SAADC: Events are not generated when switching from scan mode to no-scan mode
[29] Debug and Trace: System reset does not work
[30] PWM: False SEQEND[0] and SEQEND[1] events are generated
[31] LFXO: LFXO startup fails
[32] Debug and Trace: Debug power-up request is not acknowledged
[33] DPPI: Non-secure code can detect secure events
[36] Debug and Trace: Access port gets locked in WFI and WFE

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