PHY.CLOCK

Address offset: 0x444

USB PHY clock configurations


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															C	B	A	A	A
Reset 0x0000001A				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0	1	0
ID	R/W	Field	Value ID	Value								Description
A	RW	FSEL										Select reference clock frequency
			Clock19200KHz	0								Reference clock is 19.2MHz. The PLLBTUNE must be set to 1.
			Clock20000KHz	1								Reference clock is 20MHz. The PLLBTUNE must be set to 1.
			Clock24000KHz	2								Reference clock is 24MHz. The PLLBTUNE must be set to 1.
			Clock50000KHz	7								Reference clock is 50MHz. The PLLBTUNE must be set to 0.
B	RW	PLLBTUNE										PLL bandwidth adjustment
			Disabled	0								PLL bandwidth adjustment disabled.
			Enabled	1								PLL bandwidth adjustment enabled.
C	RW	COMMONONN										Common block power down control
			POWERED	0								The REFCLOCK_LOGIC,bias and PLL blocks are powered in sleep or suspend mode.
			SUSPEND	1								The REFCLOCK_LOGIC, bias and PLL blocks are powered down in suspend mode and bias and PLL blocks are powered down in sleep mode.