This section describes nRF7002 hardware and layout specifications.

Pin assignments

The pin assignment figure and tables describe the pinouts for the device. There are also recommendations for how the General-Purpose Input/Output (GPIO) pins should be configured, in addition to any usage restrictions.

Pin assignments for the nRF7002 QFN package

Figure 1. Pin assignments for the QFN 6 x 6 mm package.
Pin assignments (QFN)
Table 1. Pin assignments (QFN package)
Pin Name Function Description
1 OTPVDD Power
2 N.C. Do not connect
3 N.C. Do not connect
4 N.C. Do not connect
5 N.C. Do not connect
6 N.C. Do not connect
7 TXRF<1> RF 5 GHz
8 PAVDD<1> Power
9 TXRF<0> RF 2.4 GHz
10 PAVDD<0> Power
11 SXLDO Power
12 PALDO Power
13 VBAT Power
14 RFVDD Power
15 RFBUCKVDD Power
16 XOLDO Power
17 XOP Analog input 40 MHz crystal (or TCXO output if using an external TCXO)
18 XON Analog input 40 MHz crystal (or N.C. if using an external TCXO)
19 AFELDO Power
20 AFEVBAT Power
21 N.C. Do not connect
22 N.C. Do not connect
23 N.C. Do not connect
24 N.C. Do not connect
25 BUCKVBAT Power
26 BUCKOUT Power DCDC output
27 BUCKVSS Power DCDC GND
28 BUCKVSS Power DCDC GND
29 BUCKVMID Power Voltage reference decoupling pin
30 BUCKEN Digital I/O PWR IP enable pin
31 BUCKVBATS Power
32 PWRBUCKVDD Power
33 DIGVDD Power
34 PWRIOVDD Power
35 QSPI_CLK

SPI_CLK

 Digital I/O QSPI Clock

SPI Clock
36 QSPI_SS

SPI_SS

 Digital I/O QSPI Slave select

SPI Slave select
37 QSPI_DATA0

SPI_MOSI

 Digital I/O QSPI data

SPI data
38 QSPI_DATA1

SPI_MISO

 Digital I/O QSPI data

SPI data
39 QSPI_DATA2 Digital I/O QSPI data
40 QSPI_DATA3 Digital I/O QSPI data
41 COEX_STATUS0 Digital I/O Coex interface
42 COEX_REQ Digital I/O Coex interface
43 COEX_GRANT Digital I/O Coex interface
44 SW_CTRL0 Digital I/O External switch control
45 SW_CTRL1 Digital I/O External switch control
46 HOST_IRQ Digital I/O Host processor interrupt request
47 VSS Power
48 IOVDD Power
49 (Die pad) VSS Power Ground pad. Exposed die pad must be connected to ground (VSS) for proper device operation.

Pin assignment for the nRF7002 WLCSP package

Figure 2. Pin assignments for the WLCSP package.
Pin assignments (WLCSP)
Table 2. Pin assignments (WLCSP package)
Pin Name Function Description
J5 BUCKEN Digital I/O PWR IP enable pin
K11 XOP Analog input 40 MHz crystal (or TCXO output if using an external TCXO)
L11 XON Analog input 40 MHz crystal (or N.C. if using an external TCXO)
A3 QSPI_DATA2 Digital I/O QSPI data
A9 SW_CTRL1 Digital I/O External switch control
A11 COEX_GRANT Digital I/O Coex interface
A16 SW_CTRL0 Digital I/O External switch control
B2 QSPI_DATA0

SPI_MOSI

 Digital I/O QSPI data

SPI data
B4 QSPI_DATA1

SPI_MISO

 Digital I/O QSPI data

SPI data
B6 QSPI_DATA3 Digital I/O QSPI data
A5 COEX_REQ Digital I/O Coex interface
B10 HOST_IRQ Digital I/O Host processor interrupt request
B12 IOVDD Power
B8 COEX_STATUS0 Digital I/O Coex interface
C1 QSPI_CLK

SPI_CLK

 Digital I/O QSPI Clock

SPI Clock
C3 QSPI_SS

SPI_SS

 Digital I/O QSPI Slave select

SPI Slave select
K3 BUCKOUT Power DCDC output
L1 BUCKVBAT Power
J1 BUCKVSSS Power DCDC silent GND. Must be connected to global ground (VSS) for proper device operation.
K1 BUCKVSS Power DCDC GND
B17 OTPVDD Power
D3 PWRIOVDD Power
E16 PAVDD<1> Power
F1 DIGVDD Power
F3 PWRBUCKVDD Power
F5 BUCKVBATS Power
J11 XOLDO Power
J14 PAVDD<0> Power
J3 BUCKVMID Power Voltage reference decoupling pin
J9 AFELDO Power
K9 AFEVBAT Power
K13 RFVDD Power
K16 SXLDO Power
L13 RFBUCKVDD Power
L16 VBAT Power
L20 PALDO Power
D18 TXRF<1> RF 5 GHz
G16 TXRF<0> RF 2.4 GHz
A1, A7, A13, A18, A20, C5, C7, C9, C11, C13, D1, D5, D7, D9, D11, D13, D16, D20, E3, E5, E7, E9, E11, E13, F7, F9, F11, F13, H20, J7, K20, L3, L9, L18 VSS Power Chip GND. Must be connected to global ground (VSS) for proper device operation.
B15, B19, C16, C18, C20, K5, K7, L5, L7 N.C. Do not connect

Mechanical specifications

The mechanical specifications for the packages show the dimensions in millimeters.

QFN 6 x 6 mm package

Dimensions in millimeters for the QFN 6 x 6 mm package.

Table 3. QFN package dimensions in millimeters
A A1 A2 A3 b D E D2 E2 e K L
Min. 0.8 0.15 5.9 5.9 0.2 0.35
Nom. 0.85 0.035 0.65 0.203 0.2 6 6 4.6 4.6 0.4 0.4
Max. 0.9 0.05 0.25 6.1 6.1 0.45

WLCSP package

Dimensions in millimeters for the WLCSP package.

Table 4. WLCSP package dimensions in millimeters
A A1 A2 D E D1 E1 e b n
Min. 0.422 0.125 0.297 0.19
Nom. 0.48 0.325 3.7495 3.385 3.1509 2.8008 0.3501 81
Max. 0.538 0.185 0.353 0.25

Reference circuitry

To ensure good RF performance when designing Printed Circuit Board (PCB)s, it is highly recommended to use the PCB layouts and component values provided by Nordic Semiconductor.

Reference schematic (QFN)

Circuit configuration, showing the schematic and Bill of Materials (BOM) table for nRF7002 QFN package.

Figure 3. nRF7002 reference schematic (QFN)
image/svg+xml I R Q S W _ C T R L 1 S W _ C T R L 0 C O E X _ G R A N T C O E X _ S T A T U S C O E X _ R E Q Q S P I _ D A T A 3 Q S P I _ D A T A 2 Q S P I _ D A T A 1 / S P I _ M I S O VDDIO Q S P I _ D A T A 0 / S P I _ M O S I Q S P I _ S S / S P I _ S S Q S P I _ C L K / S P I _ C L K C18 2.2 µ F OTPVDD 1 NC 2 NC 3 NC 4 NC 5 NC 6 TXRF1 7 PAVDD1 8 TXRF0 9 PAVDD0 10 SXLDO 11 PALDO 12 V B A T 1 3 R F V D D 1 4 R F B U C K V D D 1 5 X O L D O 1 6 X O P 1 7 X O N 1 8 A F E L D O 1 9 A F E V B A T 2 0 N C 2 1 N C 2 2 N C 2 3 N C 2 4 BUCKVBAT 25 BUCKOUT 26 BUCKVSS 27 BUCKVSS 28 BUCKVMID 29 BUCKEN 30 BUCKVBATS 31 PWRBUCKVDD 32 DIGVDD 33 PWRIOVDD 34 Q S P I _ C L K 3 5 Q S P I _ S S 3 6 Q S P I _ D A T A 0 3 7 Q S P I _ D A T A 1 3 8 Q S P I _ D A T A 2 3 9 Q S P I _ D A T A 3 4 0 C O E X _ R E Q 4 2 C O E X _ S T A T U S 0 4 1 C O E X _ G R A N T 4 3 S W _ C T R L 0 4 4 S W _ C T R L 1 4 5 H O S T _ I R Q 4 6 V S S 4 7 I O V D D 4 8 V S S 4 9 nRF7002 U1 nRF7002-QFAA PWRIOVDD PWRIOVDD C9 2.2 µ F C17 100nF A N T C10 1.0 µ F C4 0.47 µ F TXRF1 VBAT BUCK_EN TXRF0 SXLDO VDD_BUCK L1 3.3 µ H PALDO C12 100nF C7 2.2 µ F C8 10nF C11 4.7 µ F C14 0.47 µ F C1 4.7 µ F C2 4.7 µ F VBAT VDD_BUCK VBAT C3 0.22 µ F C5 1.0 µ F C6 4.7 µ F C13 22nF C15 2.2 µ F C16 1.0 µ F VBAT X1 40MHz Connect to an isolated metal plane on top layer with vias to isolated metal plane on layer2 connecting only near thermal vias on the IC Paddle. See the layout in layer2. 2.4G 1 GND 2 5G 3 GND 5 COM 6 GND 7 U2 Diplexer
Table 5. BOM for nRF7002 (QFN)
Designator Value Description Note
U1 nRF7002-QFAA Wi-Fi® 6 Dual Band companion chip
U2 2.4 / 5 GHz WLAN Dual Band Diplexer
X1 40 MHz Crystal SMD 1612, 40 MHz, Cl=8 pF ESR max 100 Ω
L1 3.3 µH Inductor, 1 A, ±20%, 200 mΩ
C1, C2, C6, C11 4.7 µF Capacitor, Ceramic, 4.7 µF 25 V X6S 0603, ±10%

Place C1 close to BUCKVBAT pin

Place C2 close to L1

Place C11 close to PALDO pin
C3 0.22 uF Capacitor, Ceramic, 0.22 µF 10 V X5R 0201, ±10%

Place C3 close to RFBUCKVDD pin
C4, C14 0.47 uF Capacitor, Ceramic, 0.47 µF 6.3 V X5R 0201, ±10%

Place C4 close to PWRBUCKVDD pin
C5 1.0 µF Capacitor, Ceramic, 1.0 µF 35 V X5R 0402, ±10%
C7, C18 2.2 µF Capacitor, Ceramic, 2.2 µF 16 V X7S 0603, ±10%

Place C7 close to BUCKVBATS pin
C8 10 nF Capacitor, Ceramic, 10 nF 16 V X7R 0201, ±10%
C9 2.2 µF Capacitor, Ceramic, 2.2 µF 25 V X5R 0402, ±10%
C10 1.0 µF Capacitor, Ceramic, 1.0 µF 16 V X6S 0402, ±10%
C12 100 nF Capacitor, Ceramic, 100 nF 16 V X7S 0201, ±10%

Place C12 close to PAVDD0 pin
C13 22 nF Capacitor, Ceramic, 22 nF 10 V X5R 0201, ±10%
C15 2.2 µF Capacitor, Ceramic, 2.2 µF 10 V X5R 0201, ±10%
C16 1.0 µF Capacitor, Ceramic, 1.0 µF 10 V X7S 0402, ±10%
C17 100 nF Capacitor, Ceramic, 100 nF 16 V X7S 0201, ±10%

PCB layout example (QFN)

The PCB layout in this section is a reference layout for the QFN package.

It is highly recommended to use the layout example as presented with the following boundary clarifications:
  • Keep the antenna connection short.
  • Connect VBAT supply to component C6 in the bottom layer.
  • Connect IOVDD supply to component C18 in the bottom layer.
Figure 4. Top silk layer
Top silk layer
Figure 5. Top layer
Top layer
Figure 6. Mid layer 1
Mid layer 1
Figure 7. Mid layer 2
Mid layer 2
Figure 8. Bottom layer
Bottom layer

Reference schematic (WLCSP)

Circuit configuration, showing the schematic and Bill of Materials (BOM) table for nRF7002 WLCSP package.

Figure 9. nRF7002 reference schematic (WLCSP)
image/svg+xml
Table 6. BOM for nRF7002 (WLCSP)
Designator Value Description Note
U1 nRF7002-CEAA Wi-Fi 6 Dual Band companion chip WLCSP
F1 Signal Conditioning 2.4GHz and 5GHz Diplexer
X1 40 MHz Crystal SMD 1612, 40 MHz, Cl=8 pF ESR max 100 Ω
L1 3.3 µH Inductor, 1 A, ±20%, 200 mΩ
C1, C2, C6, C11 4.7 µF Capacitor, Ceramic, 4.7 µF 25 V X6S 0603, ±10%

Place C1 close to BUCKVBAT pin

Place C2 close to inductor L1

Place C11 close to PALDO pin
C3 0.22 uF Capacitor, Ceramic, 0.22 µF 10 V X5R 0201, ±10%

Place C3 close to RFBUCKVDD pin
C4, C14 0.47 uF Capacitor, Ceramic, 0.47 µF 6.3 V X5R 0201, ±10%

Place C4 close to PWRBUCKVDD pin
C5 1.0 µF Capacitor, Ceramic, 1.0 µF 35 V X5R 0402, ±10%
C7 2.2 µF Capacitor, Ceramic, 2.2 µF 16 V X7S 0603, ±10%

Place C7 close to BUCKVBATS pin
C8 10 nF Capacitor, Ceramic, 10 nF 16 V X7R 0201, ±10%
C9, C18 2.2 µF Capacitor, Ceramic, 2.2 µF 25 V X5R 0402, ±10%
C10 1.0 µF Capacitor, Ceramic, 1.0 µF 16 V X6S 0402, ±10%
C12, C17 100 nF Capacitor, Ceramic, 100 nF 16 V X7S 0201, ±10%

Place C12 close to PAVDD0 pin
C13 22 nF Capacitor, Ceramic, 22 nF 10 V X5R 0201, ±10%
C15 2.2 µF Capacitor, Ceramic, 2.2 µF 10 V X5R 0201, ±10%
C16 1.0 µF Capacitor, Ceramic, 1.0 µF 10 V X7S 0402, ±10%

PCB layout example (WLCSP)

The PCB layout in this section is a reference layout for the WLCSP package.

It is highly recommended to use the layout example as presented with the following boundary clarifications:
  • Keep the antenna connection short.
  • Connect VBAT supply to component C6 in the bottom layer.
  • Connect IOVDD supply to component C18 in the bottom layer.
  • Preferred stack up for wlcsp board is 1 mm.
Figure 10. Top silk layer
Top silk layer
Figure 11. Top layer
Top layer
Figure 12. Mid layer 1
Mid layer 1
Figure 13. Mid layer 2
Mid layer 2
Figure 14. Bottom layer
Bottom layer

Supply sequencing requirements

The various supplies and BUCKEN need to be sequenced in order with delay requirements.

The power up sequence and requirements are:

  • Supply VBAT/BUCKVBAT/BUCKVBATS/AFEVBAT
  • Wait ≥ 6 ms
  • Assert BUCKEN
  • Wait ≥ 1 ms
  • Supply IOVDD

PWRIOVDD is an internally generated supply, used for supplying OTPVDD through an external connection. It cannot be used for anything else. This supply is automatically controlled in the device.

The power-down sequence and requirements are:

  • De-assert BUCKEN and power down IOVDD
  • Power down VBAT

There are no specific timing delay requirements as long as the sequence is correct.

Supply system alternatives

nRF7002 can be powered up/down from a host dynamically. This dynamic control uses the BUCKEN pin and an external switch to control the IOVDD supply. Both the BUCKEN pin and the external switch control are driven from a GPIO on the host, controlled by the Wi-Fi driver.

There are two options (high voltage and normal voltage) for connecting nRF7002 to an nRF5340 host, supporting dynamic powerup/powerdown of the nRF7002. This dynamic control utilises an external switch to control the IOVDD supply.

The following figure shows the recommended connection between nRF7002 and the host Microcontroller Unit (MCU) (nRF5340).

Figure 15. Supply system - high voltage mode
Supply system - high voltage mode

Both nRF5340 (used in high voltage mode) and nRF7002 can be supplied from a single 3.6 V supply.

nRF5340 can provide a 1.8 V supply used for the IO supply on nRF7002. An external switch is used to disconnect IOVDD on nRF7002 when not in use. The control of the switch is handled by the Wi-Fi driver on nRF5340.

Figure 16. Supply system - normal voltage mode
Supply system - normal voltage mode

QSPI/SPI connections

The nRF7002 can be connected to the nRF5340 host either with a Quad Serial Peripheral Interface (QSPI) or a Serial Peripheral Interface (SPI). QSPI is normally the preferred option, but in cases where QSPI on the host is used for other purposes SPI can be used.

The following figure shows the connection using QSPI between nRF7002 and the host MCU (nRF5340).

Figure 17. QSPI connection
QSPI connection

The following figure shows the connections using SPI between nRF7002 and nRF5340.

Figure 18. SPI connection
SPI interface connection

TCXO connection

It is possible to use an external TCXO instead of a crystal.

This option does not require production line trimming, but it will draw more current and hence significantly degrade sleep performance. The TCXO should be disabled when in Shutdown mode to reduce current consumption. It is not possible to dynamically control the TCXO when transitioning between Sleep and Active states. The TCXO should have a typical clipped sine wave output of 0.4 V peak (maximum 0.6 V peak) and be connected through a series capacitor (typically 10 nF).