Some of the GPIOs on the nRF5340 System on Chip (SoC) are routed to test points for test purposes or to connectors to enable to connect to external hardware. The following sections describe these connectors and test points.
The trace functionality through the current
measurement and debug board, Serial Wire Debug (SWD) interface, and expansion
board interface (4-pin JST connector) are disabled by software in the factory-programmed
firmware. These features can be enabled by custom firmware, but such modification may
void the FCC authorization of the device. See Regulatory notices.