The Factory Information Configuration Registers (FICR) are stored in the One Time Programmable (OTP) memory.

FICR has two regions:

  • A factory-programmed region that contains device information and has the INFO group registers.
  • A customer-programmable region that contains empty registers for the customer to write data to. It has the QSPI, MAC, and CALIB group registers.

Access to the customer-programmable region is controlled using the PROTECTION register.

The PROTECTION scenarios are:
  • When PROTECTION is unprogrammed, neither read not write is enabled.
  • When PROTECTION is programmed to 0x50FA50FA, full read and write access is enabled.
  • When PROTECTION is programmed to 0x00000000, access protection is applied and readout of QSPI.KEY is prevented.

The following table shows the access protection for the different register groups.

Table 1. PROTECTION register settings for access control to customer programmable region
Register group 0xFFFFFFFF 0x50FA50FA 0x00000000
QSPI.KEY - R/W -
MAC.ADDRESS - R/W R
CALIB - R/W R

Registers

Register overview

Register Offset Description
INFO.PART 0x0C0

Part code
INFO.VARIANT 0x0C4

Part variant
INFO.UUID[n] 0x0D0

Universal Unique ID
REGION.PROTECT[n] 0x100

Region protection
QSPI.KEY[n] 0x110

QSPI link symmetric encryption key (ENC.KEY)
MAC[n].ADDRESS0 0x120

MAC address for VIFn
MAC[n].ADDRESS1 0x124

MAC address for VIFn
CALIB.XO 0x130

XO adjustment
REGION_DEFAULTS 0x154

Customer region register usage indicator
USERDATA[n] 0x198

User data region

INFO.PART

Address offset: 0x0C0

Part code

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

R

PART

Part code

N7000

0x7000

nRF7000

INFO.VARIANT

Address offset: 0x0C4

Part variant

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

R

VARIANT

Part Variant, Hardware version and Production configuration, encoded as ASCII

A00

0x413030

A00

INFO.UUID[n] (n=0..3)

Address offset: 0x0D0 + (n × 0x4)

Universal Unique ID

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

R

UUID

Universal Unique ID

REGION.PROTECT[n] (n=0..3)

Address offset: 0x100 + (n × 0x4)

Region protection

Used to set access restrictions for FICR. Refer to description in top of chapter. All 4 registers need to be set to the same value to change protection state.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

VALUE

Protection value

Undefined

0xFFFFFFFF

Undefined

Open

0x50FA50FA

Open

Restricted

0x00000000

Restricted

QSPI.KEY[n] (n=0..3)

Address offset: 0x110 + (n × 0x4)

QSPI link symmetric encryption key (ENC.KEY)

KEY[0] represent key bits 31:0, KEY[1] is bits 63:32, KEY[2] is bits 95:64, KEY[3] is bits 127:96

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

KEY

QSPI link symmetric encryption key

MAC[n].ADDRESS0 (n=0..1)

Address offset: 0x120 + (n × 0x8)

MAC address for VIFn

Most significant 4 bytes of MAC address b6:b5:b4:b3:b2:b1

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

R

b6

6th byte (b6) of MAC address
B

R

b5

5th byte (b5) of MAC address
C

R

b4

4th byte (b4) of MAC address
D

R

b3

3rd byte (b3) of MAC address

MAC[n].ADDRESS1 (n=0..1)

Address offset: 0x124 + (n × 0x8)

MAC address for VIFn

Least significant 2 bytes of MAC address b6:b5:b4:b3:b2:b1

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B B B B B B B B A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

R

b2

2nd byte (b2) of MAC address
B

R

b1

1st byte (b1) of MAC address

CALIB.XO

Address offset: 0x130

XO adjustment

Adjusts capacitor bank, 0 : Lowest capacitance (Highest frequency), 127 : Highest capacitance (Lowest frequency)

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

XO

XO adjustment

REGION_DEFAULTS

Address offset: 0x154

Customer region register usage indicator

Bit set to '0' indicate corresponding register is programmed

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID D C B A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

QSPIKEY

QSPI.KEY state
B

RW

MAC0ADDRESS

MAC0.ADDRESS state
C

RW

MAC1ADDRESS

MAC1.ADDRESS state
D

RW

XO

CALIB.XO state

USERDATA[n] (n=0..25)

Address offset: 0x198 + (n × 0x4)

User data region

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

DATA

Data