Reference circuitry

nRF52810 Product Specification

To ensure good RF performance when designing PCBs, it is highly recommended to use the PCB layouts and component values provided by Nordic Semiconductor.

Documentation for the different package reference circuits, including Altium Designer files, PCB layout files, and PCB production files can be downloaded from the product page for the nRF52810 on www.nordicsemi.com.

Schematic QFAA QFN48 with internal LDO regulator setup

In addition to the schematic, the bill of material (BOM) is also provided.

Figure 1. QFAA QFN48 with internal LDO regulator setup
image/svg+xml1 1 2 2 3 3 4 4 D D C C B B A A Title Size Project Number Date: File: Sheet of Drawn By: Revision nRF52810-QFAA Reference Layout 0.1 18.08.2017 nrf52810_qfaa.SchDoc 1 1 RUBR A4 C1 12pF C2 12pF C7 100pF C9 4.7 µ F C4 100nF C5 100nF XC1 XC2 VDD_nRF P0.07 P0.08 P0.10 P 0 . 1 1 P 0 . 1 2 P 0 . 1 3 P 0 . 1 4 P 0 . 1 7 P 0 . 1 8 P 0 . 1 9 P 0 . 2 0 P 0 . 2 1 P0.22 P0.23 P0.24 P 0 . 2 5 DEC1 P 0 . 2 8 / A I N 4 P 0 . 2 9 / A I N 5 SWDCLK SWDIO C10 1.0 µ F P0.06 RF C3 0.8pF C8 100nF L1 3.9nH C6 N.C. P0.00/XL1 P0.01/XL2 P 0 . 2 7 P 0 . 2 6 VDD_nRF VDD_nRF DEC3 P0.02/AIN0 P0.03/AIN1 P0.04/AIN2 P0.05/AIN3 P 0 . 1 5 P 0 . 1 6 P0.09 D E C 4 P 0 . 3 0 / A I N 6 P 0 . 3 1 / A I N 7 DEC2 C12 12pF C11 12pF Optional X1 32MHz X2 32.768kHz DEC1 1 P0.10 12 V D D 1 3 VSS 31 ANT 30 DEC2 32 DEC3 33 XC1 34 XC2 35 VDD 36 P 0 . 2 5 3 7 P 0 . 2 6 3 8 P0.00/XL1 2 P0.01/XL2 3 P0.02/AIN0 4 P0.03/AIN1 5 P0.04/AIN2 6 P0.05/AIN3 7 P0.06 8 P0.07 9 P0.08 10 P0.09 11 P 0 . 1 1 1 4 P 0 . 1 2 1 5 P 0 . 1 3 1 6 P 0 . 1 4 1 7 P 0 . 2 7 3 9 P 0 . 2 8 / A I N 4 4 0 P 0 . 2 9 / A I N 5 4 1 P 0 . 3 0 / A I N 6 4 2 P 0 . 3 1 / A I N 7 4 3 N . C . 4 4 D E C 4 4 6 V S S 4 5 V D D 4 8 D C C 4 7 SWDCLK 25 SWDIO 26 P0.22 27 P0.23 28 P0.24 29 P 0 . 1 5 1 8 P 0 . 1 6 1 9 P 0 . 1 7 2 0 P 0 . 1 8 2 1 P 0 . 2 0 2 3 P 0 . 2 1 / R E S E T 2 4 P 0 . 1 9 2 2 nRF52810 U1 nRF52810-QFAA

Note: For PCB reference layouts, see the product page for the nRF52810 on www.nordicsemi.com.
Table 1. Bill of material for QFAA QFN48 with internal LDO regulator setup
Designator Value Description Footprint
C1, C2, C11, C12 12 pF Capacitor, NP0, ±2% 0402
C3 0.8 pF Capacitor, NP0, ±5% 0402
C4, C5, C8 100 nF Capacitor, X7R, ±10% 0402
C6 N.C. Not mounted 0402
C7 100 pF Capacitor, NP0, ±5% 0402
C9 4.7 µF Capacitor, X5R, ±10% 0603
C10 1.0 µF Capacitor, X7R, ±10% 0603
L1 3.9 nH High frequency chip inductor ±5% 0402
U1 nRF52810-QFAA Multiprotocol Bluetooth® low energy, ANT, and 2.4 GHz proprietary System on Chip QFN-48
X1 32 MHz XTAL SMD 2016, 32 MHz, Cl = 8 pF, Total Tol: ±40 ppm XTAL_2016
X2 32.768 kHz XTAL SMD 3215, 32.768 kHz, Cl = 9 pF, Total Tol: ±20 ppm XTAL_3215

Schematic QFAA QFN48 with DC/DC regulator setup

In addition to the schematic, the bill of material (BOM) is also provided.

Figure 2. QFAA QFN48 with DC/DC regulator setup
image/svg+xml1 1 2 2 3 3 4 4 D D C C B B A A Title Size Project Number Date: File: Sheet of Drawn By: Revision nRF52810-QFAA Reference Layout (DCDC) 0.1 18.08.2017 nrf52810_qfaa_dcdc.SchDoc 1 1 RUBR A4 X1 32MHz C1 12pF C2 12pF C7 100pF C9 4.7 µ F C4 100nF C5 100nF XC1 XC2 VDD_nRF P0.07 P0.08 P0.10 P 0 . 1 1 P 0 . 1 2 P 0 . 1 3 P 0 . 1 4 P 0 . 1 7 P 0 . 1 8 P 0 . 1 9 P 0 . 2 0 P 0 . 2 1 P0.22 P0.23 P0.24 P 0 . 2 5 DEC1 P 0 . 2 8 / A I N 4 P 0 . 2 9 / A I N 5 SWDCLK SWDIO L2 10 µ H C10 1.0 µ F L3 15nH P0.06 RF C3 0.8pF C8 100nF L1 3.9nH C6 N.C. P0.00/XL1 P0.01/XL2 P 0 . 2 7 P 0 . 2 6 VDD_nRF DEC1 1 P0.10 12 V D D 1 3 VSS 31 ANT 30 DEC2 32 DEC3 33 XC1 34 XC2 35 VDD 36 P 0 . 2 5 3 7 P 0 . 2 6 3 8 P0.00/XL1 2 P0.01/XL2 3 P0.02/AIN0 4 P0.03/AIN1 5 P0.04/AIN2 6 P0.05/AIN3 7 P0.06 8 P0.07 9 P0.08 10 P0.09 11 P 0 . 1 1 1 4 P 0 . 1 2 1 5 P 0 . 1 3 1 6 P 0 . 1 4 1 7 P 0 . 2 7 3 9 P 0 . 2 8 / A I N 4 4 0 P 0 . 2 9 / A I N 5 4 1 P 0 . 3 0 / A I N 6 4 2 P 0 . 3 1 / A I N 7 4 3 N . C . 4 4 D E C 4 4 6 V S S 4 5 V D D 4 8 D C C 4 7 SWDCLK 25 SWDIO 26 P0.22 27 P0.23 28 P0.24 29 P 0 . 1 5 1 8 P 0 . 1 6 1 9 P 0 . 1 7 2 0 P 0 . 1 8 2 1 P 0 . 2 0 2 3 P 0 . 2 1 / R E S E T 2 4 P 0 . 1 9 2 2 nRF52810 U1 nRF52810-QFAA VDD_nRF DEC3 P0.02/AIN0 P0.03/AIN1 P0.04/AIN2 P0.05/AIN3 P 0 . 1 5 P 0 . 1 6 P0.09 D E C 4 P 0 . 3 0 / A I N 6 P 0 . 3 1 / A I N 7 DEC2 C12 12pF C11 12pF X2 32.768kHz Optional

Note: For PCB reference layouts, see the product page for the nRF52810 on www.nordicsemi.com.
Table 2. Bill of material for QFAA QFN48 with DC/DC regulator setup
Designator Value Description Footprint
C1, C2, C11, C12 12 pF Capacitor, NP0, ±2% 0402
C3 0.8 pF Capacitor, NP0, ±5% 0402
C4, C5, C8 100 nF Capacitor, X7R, ±10% 0402
C6 N.C. Not mounted 0402
C7 100 pF Capacitor, NP0, ±5% 0402
C9 4.7 µF Capacitor, X5R, ±10% 0603
C10 1.0 µF Capacitor, X7R, ±10% 0603
L1 3.9 nH High frequency chip inductor ±5% 0402
L2 10 µH Chip inductor, IDC,min = 50 mA, ±20% 0603
L3 15 nH High frequency chip inductor ±10% 0402
U1 nRF52810-QFAA Multiprotocol Bluetooth® low energy, ANT, and 2.4 GHz proprietary System on Chip QFN-48
X1 32 MHz XTAL SMD 2016, 32 MHz, Cl = 8 pF, Total Tol: ±40 ppm XTAL_2016
X2 32.768 kHz XTAL SMD 3215, 32.768 kHz, Cl = 9 pF, Total Tol: ±20 ppm XTAL_3215

Schematic QCAA QFN32 with internal LDO regulator setup

In addition to the schematic, the bill of material (BOM) is also provided.

Figure 3. QCAA QFN32 with internal LDO regulator setup
image/svg+xml1 1 2 2 3 3 4 4 D D C C B B A A Title Size Project Number Date: File: Sheet of Drawn By: Revision nRF52832-QCAA Reference Layout 1.0 26.09.2017 nrf52810_qcaa.SchDoc 1 1 RUBR A4 C1 12pF C2 12pF C7 100pF C9 4.7 µ F C4 100nF C5 100nF XC1 XC2 VDD_nRF P0.10 P 0 . 1 2 P 0 . 1 4 P 0 . 1 8 P 0 . 2 0 P 0 . 2 1 P 0 . 2 5 DEC1 P 0 . 2 8 / A I N 4 SWDCLK SWDIO C10 1.0 µ F P0.06 RF C3 0.8pF C8 100nF L1 3.9nH C6 N.C. P0.00/XL1 P0.01/XL2 VDD_nRF nRF52810 DEC1 1 P0.10 8 V D D 9 VSS 20 ANT 19 DEC2 21 DEC3 22 XC1 23 XC2 24 V D D 2 5 P 0 . 2 5 2 6 P0.00/XL1 2 P0.01/XL2 3 P0.04/AIN2 4 P0.05/AIN3 5 P0.06 6 P0.09 7 P 0 . 1 2 1 0 P 0 . 1 4 1 1 P 0 . 2 8 / A I N 4 2 7 P 0 . 3 0 / A I N 6 2 8 D E C 4 3 0 V S S 2 9 V D D 3 2 D C C 3 1 SWDCLK 17 SWDIO 18 P 0 . 1 5 1 2 P 0 . 1 6 1 3 P 0 . 1 8 1 4 P 0 . 2 0 1 5 P 0 . 2 1 / R E S E T 1 6 U1 nRF52810-QCAA VDD_nRF DEC3 P0.04/AIN2 P0.05/AIN3 P 0 . 1 5 P 0 . 1 6 P0.09 D E C 4 P 0 . 3 0 / A I N 6 DEC2 C12 12pF C11 12pF Optional X1 32MHz X2 32.768kHz

Note: For PCB reference layouts, see the product page for the nRF52810 on www.nordicsemi.com.
Table 3. Bill of material for QCAA QFN32 with internal LDO regulator setup
Designator Value Description Footprint
C1, C2, C11, C12 12 pF Capacitor, NP0, ±2% 0402
C3 0.8 pF Capacitor, NP0, ±5% 0402
C4, C5, C8 100 nF Capacitor, X7R, ±10% 0402
C6 N.C. Not mounted 0402
C7 100 pF Capacitor, NP0, ±5% 0402
C9 4.7 µF Capacitor, X5R, ±10% 0603
C10 1.0 µF Capacitor, X7R, ±10% 0603
L1 3.9 nH High frequency chip inductor ±5% 0402
U1 nRF52810-QCAA Multiprotocol Bluetooth® low energy, ANT, and 2.4 GHz proprietary System on Chip QFN-32
X1 32 MHz XTAL SMD 2016, 32 MHz, Cl = 8 pF, Total Tol: ±40 ppm XTAL_2016
X2 32.768 kHz XTAL SMD 3215, 32.768 kHz, Cl = 9 pF, Total Tol: ±20 ppm XTAL_3215

Schematic QCAA QFN32 with DC/DC regulator setup

In addition to the schematic, the bill of material (BOM) is also provided.

Figure 4. QCAA QFN32 with DC/DC regulator setup
image/svg+xml1 1 2 2 3 3 4 4 D D C C B B A A Title Size Project Number Date: File: Sheet of Drawn By: Revision nRF52832-QCAA Reference Layout (DCDC) 1.0 26.09.2017 nrf52810_qcaa_dcdc.SchDoc 1 1 RUBR A4 C1 12pF C2 12pF C7 100pF C9 4.7 µ F C4 100nF C5 100nF XC1 XC2 VDD_nRF P0.10 P 0 . 1 2 P 0 . 1 4 P 0 . 1 8 P 0 . 2 0 P 0 . 2 1 P 0 . 2 5 DEC1 P 0 . 2 8 / A I N 4 SWDCLK SWDIO L2 10 µ H C10 1.0 µ F L3 15nH P0.06 RF C3 0.8pF C8 100nF L1 3.9nH C6 N.C. P0.00/XL1 P0.01/XL2 VDD_nRF VDD_nRF DEC3 P0.04/AIN2 P0.05/AIN3 P 0 . 1 5 P 0 . 1 6 P0.09 D E C 4 P 0 . 3 0 / A I N 6 DEC2 C12 12pF C11 12pF Optional X1 32MHz X2 32.768kHz nRF52810 DEC1 1 P0.10 8 V D D 9 VSS 20 ANT 19 DEC2 21 DEC3 22 XC1 23 XC2 24 V D D 2 5 P 0 . 2 5 2 6 P0.00/XL1 2 P0.01/XL2 3 P0.04/AIN2 4 P0.05/AIN3 5 P0.06 6 P0.09 7 P 0 . 1 2 1 0 P 0 . 1 4 1 1 P 0 . 2 8 / A I N 4 2 7 P 0 . 3 0 / A I N 6 2 8 D E C 4 3 0 V S S 2 9 V D D 3 2 D C C 3 1 SWDCLK 17 SWDIO 18 P 0 . 1 5 1 2 P 0 . 1 6 1 3 P 0 . 1 8 1 4 P 0 . 2 0 1 5 P 0 . 2 1 / R E S E T 1 6 U1 nRF52810-QCAA C13 N.C.

Note: For PCB reference layouts, see the product page for the nRF52810 on www.nordicsemi.com.
Table 4. Bill of material for QCAA QFN32 with DC/DC regulator setup
Designator Value Description Footprint
C1, C2, C11, C12 12 pF Capacitor, NP0, ±2% 0402
C3 0.8 pF Capacitor, NP0, ±5% 0402
C4, C5, C8 100 nF Capacitor, X7R, ±10% 0402
C6 N.C. Not mounted 0402
C7 100 pF Capacitor, NP0, ±5% 0402
C9 4.7 µF Capacitor, X5R, ±10% 0603
C10 1.0 µF Capacitor, X7R, ±10% 0603
L1 3.9 nH High frequency chip inductor ±5% 0402
L2 10 µH Chip inductor, IDC,min = 50 mA, ±20% 0603
L3 15 nH High frequency chip inductor ±10% 0402
U1 nRF52810-QCAA Multiprotocol Bluetooth® low energy, ANT, and 2.4 GHz proprietary System on Chip QFN-32
X1 32 MHz XTAL SMD 2016, 32 MHz, Cl = 8 pF, Total Tol: ±40 ppm XTAL_2016
X2 32.768 kHz XTAL SMD 3215, 32.768 kHz, Cl = 9 pF, Total Tol: ±20 ppm XTAL_3215

Schematic CAAA WLCSP with internal LDO regulator setup

In addition to the schematic, the bill of material (BOM) is also provided.

Figure 5. CAAA WLCSP with internal LDO regulator setup
image/svg+xml1 1 2 2 3 3 4 4 D D C C B B A A Title Size Project Number Date: File: Sheet of Drawn By: Revision nRF52810-CAAA Reference Layout 1.0 26.04.2018 nrf52810_caaa.SchDoc 1 1 RUBR A4 XC1 XC2 VDD_nRF P0.08 P 0 . 1 1 P 0 . 1 2 P 0 . 1 4 P 0 . 1 7 P 0 . 1 8 P0.21/RESET DEC1 SWDCLK SWDIO P0.00/XL1 P0.01/XL2 VDD_nRF P 0 . 1 5 P 0 . 1 6 D E C 4 D E C 2 Optional X1 32MHz C1 12pF C2 12pF C10 12pF C9 12pF C7 4.7 µ F C4 100nF C5 100nF C8 1.0 µ F C6 100pF X2 32.768kHz P0.20 P0.03/AIN1 P0.04/AIN2 P0.05/AIN3 RF C3 1.2pF L1 2.2nH L2 3.3nH nRF52810 DEC1 B6 V D D G 6 VSS C1 ANT E1 D E C 2 A 3 XC1 A1 XC2 A2 P0.00/XL1 B5 P0.01/XL2 D5 P 0 . 1 2 G 5 P 0 . 1 4 F 4 D E C 4 A 4 V D D A 6 D C C A 5 SWDCLK G1 SWDIO F1 P 0 . 1 5 G 4 P 0 . 1 6 G 3 P 0 . 1 8 E 2 P0.21/RESET F2 P0.08 F6 P 0 . 1 1 F 5 VSS E4 P 0 . 1 7 F 3 P0.20 G2 VSS E3 V S S B 3 V S S D 4 P0.04/AIN2 E5 P0.03/AIN1 D6 V S S D 3 P0.05/AIN3 E6 V S S B 4 U1 nRF52810-CAAA

Note: For PCB reference layouts, see the product page for the nRF52810 on www.nordicsemi.com.
Table 5. Bill of material for CAAA WLCSP with internal LDO regulator setup
Designator Value Description Footprint
C1, C2, C9, C10 12 pF Capacitor, NP0, ±2 % 0201
C3 1.2 pF Capacitor, NP0, ±5 % 0201
C4, C5 100 nF Capacitor, X5R, ±10 % 0201
C6 100 pF Capacitor, NP0, ±2 % 0201
C7 4.7 µF Capacitor, X5R, ±10 % 0603
C8 1.0 µF Capacitor, X5R, ±5 % 0402
L1 2.2 nH High frequency chip inductor ±5 % 0201
L2 3.3 nH High frequency chip inductor ±5 % 0201
U1 nRF52810-CAAA Multiprotocol Bluetooth® low energy, ANT, and 2.4 GHz proprietary System on Chip WLCSP-33
X1 32 MHz XTAL SMD 2016, 32 MHz, Cl = 8 pF, Total Tol: ±40 ppm XTAL_2016
X2 32.768 kHz XTAL SMD 2012, 32.768 kHz, Cl = 9 pF, Total Tol: ±50 ppm XTAL_2012

Schematic CAAA WLCSP with DC/DC regulator setup

In addition to the schematic, the bill of material (BOM) is also provided.

Figure 6. CAAA WLCSP with DC/DC regulator setup
image/svg+xml1 1 2 2 3 3 4 4 D D C C B B A A Title Size Project Number Date: File: Sheet of Drawn By: Revision nRF52810-CAAA Reference Layout (DCDC) 1.0 26.04.2018 nrf52810_caaa_dcdc.SchDoc 1 1 RUBR A4 XC1 XC2 VDD_nRF P0.08 P 0 . 1 1 P 0 . 1 2 P 0 . 1 4 P 0 . 1 7 P 0 . 1 8 P0.21/RESET DEC1 SWDCLK SWDIO P0.00/XL1 P0.01/XL2 VDD_nRF P 0 . 1 5 P 0 . 1 6 D E C 4 D E C 2 Optional X1 32MHz C1 12pF C2 12pF C10 12pF C9 12pF C7 4.7 µ F C4 100nF C5 100nF L3 10 µ H C8 1.0 µ F L4 15nH C6 100pF X2 32.768kHz P0.20 P0.03/AIN1 P0.04/AIN2 P0.05/AIN3 RF C3 1.2pF L1 2.2nH L2 3.3nH nRF52810 DEC1 B6 V D D G 6 VSS C1 ANT E1 D E C 2 A 3 XC1 A1 XC2 A2 P0.00/XL1 B5 P0.01/XL2 D5 P 0 . 1 2 G 5 P 0 . 1 4 F 4 D E C 4 A 4 V D D A 6 D C C A 5 SWDCLK G1 SWDIO F1 P 0 . 1 5 G 4 P 0 . 1 6 G 3 P 0 . 1 8 E 2 P0.21/RESET F2 P0.08 F6 P 0 . 1 1 F 5 VSS E4 P 0 . 1 7 F 3 P0.20 G2 VSS E3 V S S B 3 V S S D 4 P0.04/AIN2 E5 P0.03/AIN1 D6 V S S D 3 P0.05/AIN3 E6 V S S B 4 U1 nRF52810-CAAA

Note: For PCB reference layouts, see the product page for the nRF52810 on www.nordicsemi.com.
Table 6. Bill of material for CAAA WLCSP with DC/DC regulator setup
Designator Value Description Footprint
C1, C2, C9, C10 12 pF Capacitor, NP0, ±2 % 0201
C3 1.2 pF Capacitor, NP0, ±5 % 0201
C4, C5 100 nF Capacitor, X5R, ±10 % 0201
C6 100 pF Capacitor, NP0, ±2 % 0201
C7 4.7 µF Capacitor, X5R, ±10 % 0603
C8 1.0 µF Capacitor, X5R, ±5 % 0402
L1 2.2 nH High frequency chip inductor ±5 % 0201
L2 3.3 nH High frequency chip inductor ±5 % 0201
L3 10 µH Chip inductor, IDC,min = 50 mA, ±20 % 0603
L4 15 nH High frequency chip inductor ±10 % 0402
U1 nRF52810-CAAA Multiprotocol Bluetooth® low energy, ANT, and 2.4 GHz proprietary System on Chip WLCSP-33
X1 32 MHz XTAL SMD 2016, 32 MHz, Cl = 8 pF, Total Tol: ±40 ppm XTAL_2016
X2 32.768 kHz XTAL SMD 2012, 32.768 kHz, Cl = 9 pF, Total Tol: ±50 ppm XTAL_2012

Schematic CAAA WLCSP with two layers

In addition to the schematic, the bill of material (BOM) is also provided.

Figure 7. CAAA WLCSP 2-layer setup
image/svg+xml1 1 2 2 3 3 4 4 D D C C B B A A Title Size Project Number Date: File: Sheet of Drawn By: Revision nRF52810-CAAA Reference Layout (2-Layers) 1.0 26.04.2018 nrf52810_caaa_2-layer.SchDoc 1 1 RUBR A4 XC1 XC2 VDD_nRF P0.08 P 0 . 1 2 DEC1 SWDCLK SWDIO VDD_nRF nRF52810 DEC1 B6 V D D G 6 VSS C1 ANT E1 D E C 2 A 3 XC1 A1 XC2 A2 P0.00/XL1 B5 P0.01/XL2 D5 P 0 . 1 2 G 5 P 0 . 1 4 F 4 D E C 4 A 4 V D D A 6 D C C A 5 SWDCLK G1 SWDIO F1 P 0 . 1 5 G 4 P 0 . 1 6 G 3 P 0 . 1 8 E 2 P0.21/RESET F2 P0.08 F6 P 0 . 1 1 F 5 VSS E4 P 0 . 1 7 F 3 P0.20 G2 VSS E3 V S S B 3 V S S D 4 P0.04/AIN2 E5 P0.03/AIN1 D6 V S S D 3 P0.05/AIN3 E6 V S S B 4 U1 nRF52810-CAAA P 0 . 1 5 P 0 . 1 6 D E C 4 D E C 2 X1 32MHz C1 12pF C2 12pF C7 4.7 µ F C4 100nF C5 100nF L3 10 µ H C8 1.0 µ F L4 15nH C6 100pF P0.20 P0.03/AIN1 P0.05/AIN3 RF C3 1.2pF L1 2.2nH L2 3.3nH

Note: For PCB reference layouts, see the product page for the nRF52810 on www.nordicsemi.com.
Table 7. Bill of material for CAAA WLCSP 2-layer setup
Designator Value Description Footprint
C1, C2 12 pF Capacitor, NP0, ±2 % 0201
C3 1.2 pF Capacitor, NP0, ±5 % 0201
C4, C5 100 nF Capacitor, X5R, ±10 % 0201
C6 100 pF Capacitor, NP0, ±2 % 0201
C7 4.7 µF Capacitor, X5R, ±10 % 0603
C8 1.0 µF Capacitor, X5R, ±5 % 0402
L1 2.2 nH High frequency chip inductor ±5 % 0201
L2 3.3 nH High frequency chip inductor ±5 % 0201
L3 10 µH Chip inductor, IDC,min = 50 mA, ±20 % 0603
L4 15 nH High frequency chip inductor ±10 % 0402
U1 nRF52810-CAAA Multiprotocol Bluetooth® low energy, ANT, and 2.4 GHz proprietary System on Chip WLCSP-33
X1 32 MHz XTAL SMD 2016, 32 MHz, Cl = 8 pF, Total Tol: ±40 ppm XTAL_2016

PCB guidelines

A well designed PCB is necessary to achieve good RF performance. Poor layout can lead to loss in performance or functionality.

A qualified RF layout for the IC and its surrounding components, including matching networks, can be downloaded from www.nordicsemi.com.

To ensure optimal performance it is essential that you follow the schematics and layout references closely. Especially in the case of the antenna matching circuitry (components between device pin ANT and the antenna), any changes to the layout can change the behavior, resulting in degradation of RF performance or a need to change component values. All reference circuits are designed for use with a 50 Ω single-ended antenna.

A PCB with a minimum of two layers, including a ground plane, is recommended for optimal performance. On PCBs with more than two layers, put a keep-out area on the inner layers directly below the antenna matching circuitry (components between device pin ANT and the antenna) to reduce the stray capacitances that influence RF performance.

A matching network is needed between the RF pin ANT and the antenna, to match the antenna impedance (normally 50 Ω) to the optimum RF load impedance for the chip. For optimum performance, the impedance for the matching network should be set as described in the recommended package reference circuitry in Reference circuitry.

The DC supply voltage should be decoupled as close as possible to the VDD pins with high performance RF capacitors. See the schematics for recommended decoupling capacitor values. The supply voltage for the chip should be filtered and routed separately from the supply voltages of any digital circuitry.

Long power supply lines on the PCB should be avoided. All device grounds, VDD connections, and VDD bypass capacitors must be connected as close as possible to the IC. For a PCB with a topside RF ground plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom ground plane, the best technique is to have via holes as close as possible to the VSS pads. A minimum of one via hole should be used for each VSS pin.

Fast switching digital signals should not be routed close to the crystal or the power supply lines. Capacitive loading of fast switching digital output lines should be minimized in order to avoid radio interference.

PCB layout example

The PCB layout shown in the following figures is a reference layout for the QFN48 package with internal LDO setup.

Important: Pay attention to how the capacitor C3 is grounded. It is not directly connected to the ground plane, but grounded via VSS pin 31. This is done to create additional filtering of harmonic components.

For all available reference layouts, see the product page for the nRF52810 on www.nordicsemi.com.

Figure 8. Top silk layer
Layout/image: Top silk layer

Figure 9. Top layer
Layout/image: Top layer

Figure 10. Bottom layer
Layout/image: Bottom layer

Important: No components in bottom layer.

PMIC support

The nRF52 Series is comprehensively supported by Nordic Semiconductor's own range of PMICs (Power Management Integrated Circuits). These PMICs are meticulously designed to enhance the performance and efficiency of the nRF52 Series devices. This integration ensures the longest battery life and the highest reliability for the end application. The synergy between the nRF52 Series and the Nordic PMICs highlights Nordic Semiconductor's commitment to providing a complete and cohesive solution for their customers' needs in wireless technology applications.