The device has some pins dedicated for specific purposes. GPIO pin routing and configuration is flexible. Some pins have limitations or recommendations for configuration and use.
| Peripheral | Description |
|---|---|
| TRACE | Has dedicated pins that must be configured using extra high drive E0/E1 configuration in the DRIVE0/1 fields of the PIN_CNF GPIO register. |
| GRTC | Has dedicated pins for clock and PWM output. |
| TAMPC | Has dedicated pins for active shield input and output. |
| FLPR | Uses dedicated pins on P2 for emulated peripherals such as QSPI. |
| RADIO | Uses dedicated pins on P1 for antenna switch control (DFEGPIO for direction finding). |
| NFC | Uses dedicated pins as listed in the pin assignments table for the selected device. These pins are configured as NFC antenna pins from reset. To use the pins for Digital I/O, NFC function must be disabled in the NFCT — Near field communication tag peripheral. |