Serial Peripheral Interface Slave (SPIS) timing specifications

nRF54LM20A | nRF54LM20B Datasheet

Symbol Description Min. Typ. Max. Units
tSPIS,CSCKIN

SCK input period

125 ns
tSPIS,RFSCKIN

SCK input rise/fall time

30 ns
tSPIS,WHSCKIN

SCK input high time

30 ns
tSPIS,WLSCKIN

SCK input low time

30 ns
tSPIS,SUCSN

CSN to CLK setup time

100013 ns
tSPIS,HCSN

CLK to CSN hold time

1000 ns
tSPIS,ASA

CSN to SDO driven

70 ns
tSPIS,ASO

CSN to SDO valid14

1000 ns
tSPIS,DISSO

CSN to SDO disabled14

70 ns
tSPIS,CWH

CSN inactive time

300 ns
Figure 14. SPIS timing diagram, CPHA = 0
SPIS timing diagram
Figure 15. SPIS timing diagram, CPHA = 1
SPIS timing diagram
Figure 16. Common SPIM and SPIS timing diagram
Common SPIM and SPIS timing diagram
13 Excluding any start-up delay for the high frequency clock in low power mode.
14 At 25pF load, including GPIO capacitance, see GPIO spec.