HFIR

Address offset: 0x404

Host Frame Interval Register

This register is used to control the interval between two consecutive SOFs.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																			B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x0000EA60				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	0	1	0	1	0	0	1	1	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	FRINT										Frame Interval (FrInt) The value that the application programs to this field specifies the interval between two consecutive SOFs (FS) or micro- SOFs (HS) or Keep-Alive tokens (HS). This field contains the number of PHY clocks that constitute the required frame interval. The Default value set in this field is for FS operation when the PHY clock frequency is 60 MHz. The application can write a value to this register only after the Port Enable bit of the Host Port Control and Status register (HPRT.PrtEnaPort) has been Set. If no value is programmed, the core calculates the value based on the PHY clock specified in the FS/LS PHY Clock Select field of the Host Configuration register (HCFG.FSLSPclkSel). Do not change the value of this field after the initial configuration. - 125 us * (PHY clock frequency for HS) - 1 ms * (PHY clock frequency for FS/LS)
B	RW	HFIRRLDCTRL										Reload Control (HFIRRldCtrl) This bit allows dynamic reloading of the HFIR register during run time. This bit needs to be programmed during initial configuration and its value must not be changed during runtime.
			DISABLED	0								The HFIR cannot be reloaded dynamically
			ENABLED	1								The HFIR can be dynamically reloaded during runtime