Macros |
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| #define | __NRF_NVIC_NVMC_IRQn (30) |
| #define | __NRF_NVIC_ISER_COUNT (2) |
| #define | __NRF_NVIC_SD_IRQ_PRIOS |
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Interrupt priority levels used by the SoftDevice.
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| #define | __NRF_NVIC_APP_IRQ_PRIOS ((uint8_t)~ __NRF_NVIC_SD_IRQ_PRIOS ) |
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Interrupt priority levels available to the application.
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| #define | __NRF_NVIC_SD_IRQS_0 |
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Interrupts used by the SoftDevice, with IRQn in the range 0-31.
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| #define | __NRF_NVIC_SD_IRQS_1 ((uint32_t)0) |
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Interrupts used by the SoftDevice, with IRQn in the range 32-63.
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| #define | __NRF_NVIC_APP_IRQS_0 (~ __NRF_NVIC_SD_IRQS_0 ) |
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Interrupts available for to application, with IRQn in the range 0-31.
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| #define | __NRF_NVIC_APP_IRQS_1 (~ __NRF_NVIC_SD_IRQS_1 ) |
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Interrupts available for to application, with IRQn in the range 32-63.
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Detailed Description
Macro Definition Documentation
| #define __NRF_NVIC_ISER_COUNT (2) |
The number of ISER/ICER registers in the NVIC that are used.
| #define __NRF_NVIC_NVMC_IRQn (30) |
The peripheral ID of the NVMC. IRQ numbers are used to identify peripherals, but the NVMC doesn't have an IRQ number in the MDK.
| #define __NRF_NVIC_SD_IRQ_PRIOS |
Value:
((uint8_t)( \
(1U << 0)
/**< Priority level high .*/
\
| (1U << 1)
/**< Priority level medium. */
\
| (1U << 4)
/**< Priority level low. */
\
))
Interrupt priority levels used by the SoftDevice.
| #define __NRF_NVIC_SD_IRQS_0 |
Value:
((uint32_t)( \
(1U << POWER_CLOCK_IRQn) \
| (1U << RADIO_IRQn) \
| (1U << RTC0_IRQn) \
| (1U << TIMER0_IRQn) \
| (1U << RNG_IRQn) \
| (1U << ECB_IRQn) \
| (1U << CCM_AAR_IRQn) \
| (1U << TEMP_IRQn) \
| (1U <<
__NRF_NVIC_NVMC_IRQn
) \
| (1U << (uint32_t)SWI5_IRQn) \
))
Interrupts used by the SoftDevice, with IRQn in the range 0-31.