Dedicated pins

nRF54LV10A Preliminary Datasheet

nRF54LV10A provides flexibility for routing and configuring GPIO pins, however, some pins are dedicated for specific purposes.

The following table includes recommendations for pin configuration and use.

Table 1. Dedicated pin functions
Peripheral Description
TRACE Has dedicated pins that must be configured using extra high drive H0/H1 configuration in the DRIVE0/1 fields of the PIN_CNF GPIO register.
GRTC Has dedicated pins for clock and PWM output.
TAMPC Has dedicated pins for active shield inputs and outputs.
FLPR Uses dedicated pins on P1 for emulated peripherals such as QSPI.
RADIO Uses dedicated pins on P1 for antenna switch control (DFEGPIO for direction finding).