SW-DP

nRF54LV10A Preliminary Datasheet

Symbol Description Min. Typ. Max. Units
Rpull

Internal SWDIO and SWDCLK pull up/down resistance

14
fSWDCLK

SWDCLK frequency

0.125 20 MHz
tSUI

SWDIO input setup before SWDCLK

18 ns
tHI

SWDIO input hold after SWDCLK

2 ns
tVO

SWDCLK to SWDIO output valid

67 ns
tHO

SWDIO output hold after SWDCLK

7 ns
Figure 5. SWD timing diagram
SWD timing diagram