UARTE implements a configurable data frame size of 4 bits to 9 bits and is set in the register CONFIG. If a value greater than 9 or less than 4 is written to this register, the frame size will be set to 8 bits and the register will read back a value of 8.
When UARTE is used with the 9 bit frame size, a 9th bit is added after the MSB of the 8 bit data frame, and before the parity and stop bits, as shown in the following figure. This bit indicates if the 8 bit data is an address or data. If the 9th bit is 1, the 8 bit data is interpreted as an address. If the 9th bit is 0, the 8 bit data is interpreted as data.
When UART is in RX configured with a 9 bit frame size, all frames are ignored until a frame with the address bit set is received, and the 8 remaining bits of the data frame matches the address set in the register ADDRESS. The frames following the matching address are received as an 8 bit data frame until the next frame where the address bit set is received, the address bit is not stored. If the address does not match ADDRESS, the following frames are ignored.
If the parity bit is enabled, the address bit is not included in the parity calculation.
When UART TX is started, the first byte in the buffer read by EasyDMA is treated as an address, and transmitted with the address bit set to 1. The next bits in the buffer are treated as data and transmitted with the address bit set to 0.
When UARTE uses a data frame size less than an 8 bits, the data is trimmed from an 8 bit frame size in the RAM buffer for TX, and padded before being stored in the RAM buffer for RX. The ENDIAN field in the register CONFIG defines if the data is trimmed from MSB or LSB of the 8 bit buffer frame.