CH[n].CONFIG

Address offset: 0x518 + (n × 0x10)

Input configuration for CH[m]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID					G	G	G				F	F	F	F	F	F	F	F	F	E	D	D	D								C			B	A
Reset 0x00020000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHOPPING										Enable chopping
			Disabled	0								Chopping is disabled
			Enabled	1								Chopping is enabled
B	RW	VREFPLPFDISABLE										Disable the internal low pass filter for the reference voltage Disabling the internal low pass filter enables a trade-off between faster reference voltage settling time and noise.
			Disabled	1								The internal low pass filter for the reference voltage is disabled (reference voltage is unfiltered and has faster settling time)
			Enabled	0								The internal low pass filter for the reference voltage is enabled (reference voltage is filtered)
C	RW	HIGHSPEED										Enable high speed inputs for the ADC, allowing the highest sampling bandwidth
			Disabled	0								High speed inputs are disabled
			Enabled	1								High speed inputs are enabled
D	RW	REFSEL										Reference control
			Internal	0								Internal 1.3 V reference
			External	1								External reference voltage
			VddL	2								Reference given at VDDL
E	RW	MODE										Enable differential mode
			SE	0								Single ended, PSELN will be ignored, negative input to ADC shorted to GND
			Diff	1								Differential
F	RW	TACQ		[3..319]								Acquisition time, the time the ADC uses to sample the input voltage. Resulting acquistion time is ((TACQ+1) x 125 ns)
G	RW	TCONV		[1..7]								Conversion time. Resulting conversion time is ((TCONV+1) x 250 ns)