The pin assignment figures and tables describe the pinouts for the product variants of the chip.

WLCSP ball assignments

The ball assignment figure and table describe the assignments for this variant of the chip.

Figure 1. WLCSP ball assignments (top view)
WLCSP ball assignments (top view)
Table 1. Ball assignments
Ball Name Function Description
A1 LSOUT/VOUTLDO Power LDOSW output, can be left not connected if not used
A2 VOUT Power BOOST output for the load
A3 VINT Power BOOST output, decoupling for the internal supply. No external load is allowed.
A4 PVSS Power Power ground
B1 AVSS1 Power Ground
B2 AVSS2 Power Ground
B3 VSET Analog input

BOOST output voltage selection, internal pull-up to VINT (leave pin not connected for 3.0 V or connect to ground for 1.8 V)
B4 SW Power Coil for BOOST
C1 PG/RESET Digital I/O, OD Power good/reset output, reset button input (open drain, internal pull-up to VINT). Can be left not connected if not used.
C2 SYSGDEN Digital input Leave pin not connected (boot monitor enabled) or connect to ground (boot monitor disabled) externally.
C3 GPIO0 Digital I/O

GPIO, can be left not connected if not used
C4 VBAT Power Input supply, battery voltage
D1 GPIO1 Digital I/O

GPIO, can be left not connected if not used
D2 SCL Digital input TWI clock, external pull-up connected to VOUT
D3 SDA Digital I/O TWI data, external pull-up connected to VOUT
D4 SHPHLD Analog input Wakeup from Ship mode. (Also reset button input, so called single-button case). Can be left not connected if not used.

QFN pin assignments

The pin assignment figure and table describe the assignments for this variant of the chip.

Figure 2. QFN pin assignments (top view)
QFN pin assignments (top view)
Table 2. QFN pin assignment
Pin Name Function Description
1 VSET Analog input BOOST output voltage selection, internal pull-up to VINT (leave pin not connected for 3.0 V or connect to ground for 1.8 V)
2 SW Power Coil for BOOST
3 VBAT Power Input supply, battery voltage
4 SHPHLD Analog input Wakeup from Ship mode (also reset button input, so called single-button case). Can be left not connected if not used.
5 GPIO0 Digital I/O

GPIO, can be left not connected if not used
6 SDA Digital I/O TWI data, external pull-up connected to VOUT
7 SCL Digital input TWI clock, external pull-up connected to VOUT
8 SYSGDEN Digital IN Leave pin not connected (boot monitor enabled) or connect to ground (boot monitor disabled) externally.
9 GPIO1 Digital I/O

GPIO, can be left not connected if not used
10 PG/RESET Digital I/O, OD Power good/reset output, reset button input (open drain, internal pull-up to VINT). Can be left not connected if not used.
11 AVSS2 Power Ground
12 LSOUT/VOUTLDO Power LDOSW output, can be left not connected if not used
13 VOUT Power BOOST output for the load
14 VINT Power BOOST output, decoupling for the internal supply. No external load is allowed.
15 VINT Power BOOST output, decoupling for the internal supply. No external load is allowed.
16 PVSS Power Power ground
Exposed pad AVSS1 Power Ground