Address offset: 0xA

System Interrupt Enable Set

Bit number 7 6 5 4 3 2 1 0
ID H G F E D C B A
Reset 0x00 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW
W1S

DIETWARN

Writing 1 enables interrupts from the DIETWARN event
B

RW
W1S

SHPHLDFALL

Writing 1 enables interrupts from the SHPHLDFALL event
C

RW
W1S

SHPHLDRISE

Writing 1 enables interrupts from the SHPHLDRISE event
D

RW
W1S

PGRESETFALL

Writing 1 enables interrupts from the PGRESETFALL event
E

RW
W1S

PGRESETRISE

Writing 1 enables interrupts from the PGRESETRISE event
F

RW
W1S

TIMER

Writing 1 enables interrupts from the TIMER event
G

RW
W1S

TIMERPREWRN

Writing 1 enables interrupts from the TIMERPREWRN event
H

RW
W1S

TIMERFREE

Writing 1 enables interrupts from the TIMERFREE event