XOSC32M

nRF54LV10A Preliminary Datasheet

nRF54LV10A Preliminary Datasheet
Revision history
About this document
Document status
Peripheral chapters
Peripheral naming conventions
Peripheral instantiation
Register overview table
Register tables
Fields and values
Permissions
Registers
DUMMY
Product overview
Block diagram
Memory and package overview
Power domains
Address format
Memory
RAM — Random access memory
NVM — Non-volatile memory
Memory map
Instantiation
Application core
Arm Cortex-M33 CPU
CPU
Floating point interrupt
CPU and support module configuration
CPUC — CPU control
Registers
EVENTS_FPUIOC
EVENTS_FPUDZC
EVENTS_FPUOFC
EVENTS_FPUUFC
EVENTS_FPUIXC
EVENTS_FPUIDC
INTEN
INTENSET
INTENCLR
LOCK
CPUID
Arm Cortex-M33 Peripherals
Instantiation
Core components
AMBA interconnect (AMBIX)
AMBIX00 bus Managers and priority handling
AMBIX00 override configuration
EasyDMA
EasyDMA channel implementation
EasyDMA error handling
Array list
CACHE — Instruction/data cache
Architecture
Profiling
Debug
Registers
TASKS_INVALIDATECACHE
TASKS_INVALIDATELINE
TASKS_ERASE
STATUS
ENABLE
LINEADDR
PROFILING.ENABLE
PROFILING.CLEAR
PROFILING.HIT
PROFILING.MISS
PROFILING.LMISS
PROFILING.READS
PROFILING.WRITES
DEBUGLOCK
WRITELOCK
Registers
SET[n].WAY[o].INFO
Registers
SET[n].WAY[o].DU[p].DATA[q]
FICR — Factory information configuration registers
Registers
INFO
INFO.CONFIGID
INFO.DEVICEID[n]
INFO.UUID[n]
INFO.PART
INFO.VARIANT
INFO.PACKAGE
INFO.RAM
INFO.RRAM
ER[n]
IR[n]
DEVICEADDRTYPE
DEVICEADDR[n]
TRIMCNF[n].ADDR
TRIMCNF[n].DATA
XOSC32MTRIM
XOSC32KTRIM
MEMCONF — Memory configuration
Registers
POWER[n].CONTROL
POWER[n].RET
RRAMC — Resistive random access memory controller
Reading from RRAM
Writing to RRAM
Buffered RRAM write
Erasing RRAM
Region protection
Immutable boot region
Power-failure protection
Registers
TASKS_WAKEUP
TASKS_CLRWRITEBUF
TASKS_COMMITWRITEBUF
SUBSCRIBE_WAKEUP
SUBSCRIBE_CLRWRITEBUF
SUBSCRIBE_COMMITWRITEBUF
EVENTS_WOKENUP
EVENTS_READY
EVENTS_READYNEXT
EVENTS_ACCESSERROR
PUBLISH_WOKENUP
INTEN
INTENSET
INTENCLR
INTPEND
READY
READYNEXT
ACCESSERRORADDR
BUFSTATUS.WRITEBUFEMPTY
ECC.ERRORADDR
CONFIG
READYNEXTTIMEOUT
POWER.CONFIG
POWER.LOWPOWERCONFIG
ERASE.ERASEALL
REGION[n]
REGION[n].ADDRESS
REGION[n].CONFIG
SICR — Secure information configuration region
SWI — Software interrupts
Registers
UICR — User information configuration registers
Registers
APPROTECT[n]
APPROTECT[n].PROTECT0
APPROTECT[n].PROTECT1
SECUREAPPROTECT[n]
SECUREAPPROTECT[n].PROTECT0
SECUREAPPROTECT[n].PROTECT1
AUXAPPROTECT[n]
AUXAPPROTECT[n].PROTECT0
AUXAPPROTECT[n].PROTECT1
ERASEPROTECT[n]
ERASEPROTECT[n].PROTECT0
ERASEPROTECT[n].PROTECT1
BOOTCONF
USER.ROT
USER.ROT.PUBKEY[n].DIGEST[o]
USER.ROT.PUBKEY[n].REVOKE[o]
USER.ROT.AUTHOPKEY[n].DIGEST[o]
USER.ROT.AUTHOPKEY[n].REVOKE[o]
OTP[n]
Power and clock management
System ON mode
Sub-power modes
System OFF mode
Emulated System OFF mode
System Hibernation mode
Power supply supervisors
Power-fail comparator
CLOCK — Clock control
HFCLK controller
LFCLK controller
Calibrating the 32.768 kHz RC oscillator
Registers
TASKS_XOSTART
TASKS_XOSTOP
TASKS_PLLSTART
TASKS_PLLSTOP
TASKS_LFCLKSTART
TASKS_LFCLKSTOP
TASKS_CAL
TASKS_XOTUNE
TASKS_XOTUNEABORT
SUBSCRIBE_XOSTART
SUBSCRIBE_XOSTOP
SUBSCRIBE_PLLSTART
SUBSCRIBE_PLLSTOP
SUBSCRIBE_LFCLKSTART
SUBSCRIBE_LFCLKSTOP
SUBSCRIBE_CAL
SUBSCRIBE_XOTUNE
SUBSCRIBE_XOTUNEABORT
EVENTS_XOSTARTED
EVENTS_PLLSTARTED
EVENTS_LFCLKSTARTED
EVENTS_DONE
EVENTS_XOTUNED
EVENTS_XOTUNEERROR
EVENTS_XOTUNEFAILED
PUBLISH_XOSTARTED
PUBLISH_PLLSTARTED
PUBLISH_LFCLKSTARTED
PUBLISH_DONE
PUBLISH_XOTUNED
PUBLISH_XOTUNEERROR
PUBLISH_XOTUNEFAILED
INTEN
INTENSET
INTENCLR
INTPEND
XO.RUN
XO.STAT
PLL.RUN
PLL.STAT
LFCLK.SRC
LFCLK.RUN
LFCLK.STAT
LFCLK.SRCCOPY
OSCILLATORS — Oscillator control
High-frequency (32 MHz) crystal oscillator (HFXO)
Using external capacitors
Crystal selection
Low-frequency (32.768 kHz) crystal oscillator (LFXO)
Using external capacitors
External source
CPU clock frequency selection
Registers
XOSC32M
XOSC32M.CONFIG.INTCAP
PLL
PLL.FREQ (Retained)
PLL.CURRENTFREQ (Retained)
XOSC32KI
XOSC32KI.BYPASS
XOSC32KI.INTCAP (Retained)
POWER — Power control
Registers
TASKS_CONSTLAT
TASKS_LOWPWR
SUBSCRIBE_CONSTLAT
SUBSCRIBE_LOWPWR
EVENTS_POFWARN
EVENTS_SLEEPENTER
EVENTS_SLEEPEXIT
PUBLISH_POFWARN
PUBLISH_SLEEPENTER
PUBLISH_SLEEPEXIT
INTEN
INTENSET
INTENCLR
GPREGRET[n]
CONSTLATSTAT
REGULATORS — Regulator control
VREGMAIN — Main regulator
Registers
HIBERNATOR
HIBERNATOR.SYSTEMHIBERNATE
HIBERNATOR.GPIORETENTIONRELEASE
HIBERNATOR.GPIORETENTIONSTATUS
SYSTEMOFF
POFCON (Retained)
POFSTAT
VREGMAIN
VREGMAIN.DCDCEN
VREGMAIN.INDUCTORDET
RESET — Reset control
Power-on reset
Pin reset
Brownout reset
Glitch detector
Wakeup from System OFF mode reset
Soft reset
CTRL-AP resets
Watchdog timer reset
Retained registers
Reset behavior
Registers
RESETREAS
Event system
DPPI latencies
DPPI — Distributed programmable peripheral interconnect
Channel publish and subscribe
DPPI controller (DPPIC)
Connection examples
Special considerations for a system implementing TrustZone for Cortex-M processors
Split security
Registers
TASKS_CHG[n]
TASKS_CHG[n].EN
TASKS_CHG[n].DIS
SUBSCRIBE_CHG[n]
SUBSCRIBE_CHG[n].EN
SUBSCRIBE_CHG[n].DIS
CHEN
CHENSET
CHENCLR
CHG[n]
PPIB — PPI Bridge
PPIB connections
Handshake and overflow
Connection examples
Security
Registers
TASKS_SEND[n]
SUBSCRIBE_SEND[n]
EVENTS_RECEIVE[n]
PUBLISH_RECEIVE[n]
OVERFLOW.SEND
Security
Memory and peripheral access permissions
TrustZone security
Immutable boot region
Security attributes
Security fault
Peripherals with split security access
CRACEN
DPPIC
GPIO
GPIOTE
GRTC
Physical security
Security components
CRACEN — Cryptographic accelerator engine
Disclaimer
Initialization
Protected RAM
Countermeasures
Isolated Key Generator
Loading seed to IKG
Low power
Registers
EVENTS_CRYPTOMASTER
EVENTS_RNG
EVENTS_PKEIKG
INTEN
INTENSET
INTENCLR
INTPEND
ENABLE
SEEDVALID
SEED[n]
SEEDLOCK
PROTECTEDRAMLOCK
Registers
CRYPTMSTRDMA.FETCHADDRLSB
CRYPTMSTRDMA.FETCHADDRMSB
CRYPTMSTRDMA.FETCHLEN
CRYPTMSTRDMA.FETCHTAG
CRYPTMSTRDMA.PUSHADDRLSB
CRYPTMSTRDMA.PUSHADDRMSB
CRYPTMSTRDMA.PUSHLEN
CRYPTMSTRDMA.INTEN
CRYPTMSTRDMA.INTENSET
CRYPTMSTRDMA.INTENCLR
CRYPTMSTRDMA.INTSTATRAW
CRYPTMSTRDMA.INTSTAT
CRYPTMSTRDMA.INTSTATCLR
CRYPTMSTRDMA.CONFIG
CRYPTMSTRDMA.START
CRYPTMSTRDMA.STATUS
CRYPTMSTRHW.INCLIPSHWCFG
CRYPTMSTRHW.BA411EAESHWCFG1
CRYPTMSTRHW.BA411EAESHWCFG2
CRYPTMSTRHW.BA413HASHHWCFG
CRYPTMSTRHW.BA418SHA3HWCFG
CRYPTMSTRHW.BA419SM4HWCFG
CRYPTMSTRHW.BA424ARIAHWCFG
RNGCONTROL.CONTROL
RNGCONTROL.FIFOLEVEL
RNGCONTROL.FIFOTHRESHOLD
RNGCONTROL.FIFODEPTH
RNGCONTROL.KEY[n]
RNGCONTROL.TESTDATA
RNGCONTROL.REPEATTHRESHOLD
RNGCONTROL.PROPTESTCUTOFF
RNGCONTROL.LFSRSEED
RNGCONTROL.STATUS
RNGCONTROL.WARMUPPERIOD
RNGCONTROL.DISABLEOSC
RNGCONTROL.SAMPLINGPERIOD
RNGCONTROL.HWCONFIG
RNGCONTROL.COOLDOWNPERIOD
RNGCONTROL.AUTOCORRTESTCUTOFF0
RNGCONTROL.AUTOCORRTESTCUTOFF1
RNGCONTROL.CORRTESTCUTOFF0
RNGCONTROL.CORRTESTCUTOFF1
RNGCONTROL.AUTOCORRTESTFAILED
RNGCONTROL.CORRTESTFAILED
RNGCONTROL.HWVERSION
RNGCONTROL.FIFO[n]
PK.POINTERS
PK.COMMAND
PK.CONTROL
PK.STATUS
PK.TIMER
PK.HWCONFIG
PK.OPSIZE
PK.ECCERRORBITPOS
PK.ECCCONTROLSTATUSREG
PK.MICROCODEFORMAT
PK.HWVERSION
IKG.START
IKG.STATUS
IKG.INITDATA
IKG.NONCE
IKG.PERSONALISATIONSTRING
IKG.RESEEDINTERVALLSB
IKG.RESEEDINTERVALMSB
IKG.PKECONTROL
IKG.PKECOMMAND
IKG.PKESTATUS
IKG.SOFTRST
IKG.HWCONFIG
GLITCHDET — Voltage glitch detectors
Registers
CONFIG
KMU — Key management unit
Key slot
Key slot states
Operations
Provisioning
Push
Read metadata
Revoke
Push block
Block
Error handling
Registers
TASKS_PROVISION
TASKS_PUSH
TASKS_REVOKE
TASKS_READMETADATA
TASKS_PUSHBLOCK
TASKS_BLOCK
EVENTS_PROVISIONED
EVENTS_PUSHED
EVENTS_REVOKED
EVENTS_ERROR
EVENTS_METADATAREAD
EVENTS_PUSHBLOCKED
EVENTS_BLOCKED
STATUS
KEYSLOT
SRC
METADATA
MPC — Memory Privilege Controller
Override configuration
MPC error reporting
Registers
EVENTS_MEMACCERR
INTEN
INTENSET
INTENCLR
MEMACCERR
MEMACCERR.ADDRESS
MEMACCERR.INFO
OVERRIDE[n]
OVERRIDE[n].CONFIG
OVERRIDE[n].STARTADDR
OVERRIDE[n].ENDADDR
OVERRIDE[n].PERM
OVERRIDE[n].PERMMASK
SPU — System protection unit
General concepts
Peripheral access control
Peripherals with split security
Peripheral address mapping
Special considerations for peripherals with DMA master
Peripheral access error reporting
Feature access control
Registers
EVENTS_PERIPHACCERR
INTEN
INTENSET
INTENCLR
INTPEND
PERIPHACCERR.ADDRESS
PERIPH[n].PERM
FEATURE.DPPIC.CH[n]
FEATURE.DPPIC.CHG[n]
FEATURE.GPIOTE[n].CH[o]
FEATURE.GPIOTE[n].INTERRUPT[o]
FEATURE.GPIO[n].PIN[o]
FEATURE.GRTC.CC[n]
FEATURE.GRTC.PWMCONFIG
FEATURE.GRTC.CLK
FEATURE.GRTC.SYSCOUNTER
FEATURE.GRTC.INTERRUPT[n]
TAMPC — Tamper controller
Active shield
CRACEN tamper detector
Glitch detector
Signal protector
Debugger signals
TAMPC reset behavior
Registers
EVENTS_TAMPER
EVENTS_WRITEERROR
INTEN
INTENSET
INTENCLR
INTPEND
STATUS
ACTIVESHIELD.CHEN
PROTECT.DOMAIN[n].DBGEN.CTRL
PROTECT.DOMAIN[n].DBGEN.STATUS
PROTECT.DOMAIN[n].NIDEN.CTRL
PROTECT.DOMAIN[n].NIDEN.STATUS
PROTECT.DOMAIN[n].SPIDEN.CTRL
PROTECT.DOMAIN[n].SPIDEN.STATUS
PROTECT.DOMAIN[n].SPNIDEN.CTRL
PROTECT.DOMAIN[n].SPNIDEN.STATUS
PROTECT.AP[n].DBGEN.CTRL
PROTECT.AP[n].DBGEN.STATUS
PROTECT.ACTIVESHIELD
PROTECT.ACTIVESHIELD.CTRL
PROTECT.ACTIVESHIELD.STATUS
PROTECT.CRACENTAMP
PROTECT.CRACENTAMP.CTRL
PROTECT.CRACENTAMP.STATUS
PROTECT.GLITCHSLOWDOMAIN
PROTECT.GLITCHSLOWDOMAIN.CTRL
PROTECT.GLITCHSLOWDOMAIN.STATUS
PROTECT.GLITCHFASTDOMAIN
PROTECT.GLITCHFASTDOMAIN.CTRL
PROTECT.GLITCHFASTDOMAIN.STATUS
PROTECT.EXTRESETEN
PROTECT.EXTRESETEN.CTRL
PROTECT.EXTRESETEN.STATUS
PROTECT.INTRESETEN
PROTECT.INTRESETEN.CTRL
PROTECT.INTRESETEN.STATUS
PROTECT.ERASEPROTECT
PROTECT.ERASEPROTECT.CTRL
PROTECT.ERASEPROTECT.STATUS
Peripherals
Peripheral interface
Peripheral ID
Peripherals with shared ID
Peripheral registers
Bit set and clear
Tasks
Events
Publish and subscribe
Shortcuts
Interrupts
Interrupt clearing and disabling
Instantiation
AAR — Accelerated address resolver
Shared resources
Resolving a resolvable address
EasyDMA
Use case example for chaining RADIO packet reception with address resolution using AAR
Registers
TASKS_START
TASKS_STOP
SUBSCRIBE_START
SUBSCRIBE_STOP
EVENTS_END
EVENTS_RESOLVED
EVENTS_NOTRESOLVED
EVENTS_ERROR
PUBLISH_END
PUBLISH_RESOLVED
PUBLISH_NOTRESOLVED
PUBLISH_ERROR
INTENSET
INTENCLR
ERRORSTATUS
ENABLE
MAXRESOLVED
IN
IN.PTR
OUT
OUT.PTR
OUT.AMOUNT
CCM — AES CCM mode encryption
Shared resources
Encryption and decryption
Encryption
Decryption
Encrypting packets in radio transmit mode
Decrypting packets received by the radio
CCM data structure
EasyDMA and ERROR event
Registers
TASKS_START
TASKS_STOP
TASKS_RATEOVERRIDE
SUBSCRIBE_START
SUBSCRIBE_STOP
SUBSCRIBE_RATEOVERRIDE
EVENTS_END
EVENTS_ERROR
PUBLISH_END
PUBLISH_ERROR
INTENSET
INTENCLR
MACSTATUS
ERRORSTATUS
ENABLE
MODE
KEY.VALUE[n]
NONCE.VALUE[n]
IN
IN.PTR
OUT
OUT.PTR
RATEOVERRIDE
ADATAMASK
COMP — Comparator
START and STOP tasks
Operation modes
Current source on analog input
Shared resources
Differential mode
Single-ended mode
Registers
TASKS_START
TASKS_STOP
TASKS_SAMPLE
SUBSCRIBE_START
SUBSCRIBE_STOP
SUBSCRIBE_SAMPLE
EVENTS_READY
EVENTS_DOWN
EVENTS_UP
EVENTS_CROSS
PUBLISH_READY
PUBLISH_DOWN
PUBLISH_UP
PUBLISH_CROSS
SHORTS
INTEN
INTENSET
INTENCLR
INTPEND
RESULT
ENABLE
PSEL
REFSEL
EXTREFSEL
TH
MODE
HYST
ISOURCE
ECB — AES electronic codebook mode encryption
Shared resources
EasyDMA
Registers
TASKS_START
TASKS_STOP
SUBSCRIBE_START
SUBSCRIBE_STOP
EVENTS_END
EVENTS_ERROR
PUBLISH_END
PUBLISH_ERROR
INTENSET
INTENCLR
ERRORSTATUS
KEY.VALUE[n]
IN
IN.PTR
OUT
OUT.PTR
CSAA
CSAA.REFLECTOR
CSAA.INITIATOR
CSAA.MODE
EGU — Event generator unit
Registers
TASKS_TRIGGER[n]
SUBSCRIBE_TRIGGER[n]
EVENTS_TRIGGERED[n]
PUBLISH_TRIGGERED[n]
INTEN
INTENSET
INTENCLR
GPIO — General purpose input/output
Pin configuration
Pin sense mechanism
Port capabilities
Peripheral and subsystem assignment
Clock pins
Reset behavior
Registers
OUT (Retained)
OUTSET
OUTCLR
IN
DIR (Retained)
DIRSET
DIRCLR
LATCH (Retained)
DETECTMODE (Retained)
PIN_CNF[n]
GPIOTE — GPIO tasks and events
Pin events and tasks
Port event
Tasks and events pin configuration
Split security attribute
Registers
TASKS_OUT[n]
TASKS_SET[n]
TASKS_CLR[n]
SUBSCRIBE_OUT[n]
SUBSCRIBE_SET[n]
SUBSCRIBE_CLR[n]
EVENTS_IN[n]
EVENTS_PORT[n]
EVENTS_PORT[n].NONSECURE
EVENTS_PORT[n].SECURE
PUBLISH_IN[n]
PUBLISH_PORT[n]
PUBLISH_PORT[n].NONSECURE
PUBLISH_PORT[n].SECURE
INTENSET0
INTENCLR0
INTENSET1
INTENCLR1
CONFIG[n]
GRTC — Global real-time counter
GRTC clock sources
SYSCOUNTER
Pulse Width Modulation (PWM)
Clock output
Split Security
Task priority
Registers
TASKS_CAPTURE[n]
TASKS_START
TASKS_STOP
TASKS_CLEAR
TASKS_PWMSTART
TASKS_PWMSTOP
SUBSCRIBE_CAPTURE[n]
EVENTS_COMPARE[n]
EVENTS_RTCOMPARESYNC
EVENTS_PWMPERIODEND
EVENTS_PWMREADY
EVENTS_CLKOUTREADY
PUBLISH_COMPARE[n]
PUBLISH_PWMREADY
PUBLISH_CLKOUTREADY
SHORTS
INTEN0
INTENSET0
INTENCLR0
INTPEND0
INTEN1
INTENSET1
INTENCLR1
INTPEND1
INTEN2
INTENSET2
INTENCLR2
INTPEND2
INTEN3
INTENSET3
INTENCLR3
INTPEND3
EVTEN
EVTENSET
EVTENCLR
MODE
CC[n].CCL
CC[n].CCH
CC[n].CCADD
CC[n].CCEN
TIMEOUT
INTERVAL
WAKETIME
STATUS.LFTIMER
STATUS.PWM
STATUS.CLKOUT
PWMCONFIG
CLKOUT
CLKCFG
SYSCOUNTER[n].SYSCOUNTERL
SYSCOUNTER[n].SYSCOUNTERH
SYSCOUNTER[n].ACTIVE
LPCOMP — Low-power comparator
Operation
Shared resources
Pin configuration
Registers
TASKS_START
TASKS_STOP
TASKS_SAMPLE
SUBSCRIBE_START
SUBSCRIBE_STOP
SUBSCRIBE_SAMPLE
EVENTS_READY
EVENTS_DOWN
EVENTS_UP
EVENTS_CROSS
PUBLISH_READY
PUBLISH_DOWN
PUBLISH_UP
PUBLISH_CROSS
SHORTS
INTEN
INTENSET
INTENCLR
INTPEND
RESULT
ENABLE
PSEL
REFSEL
EXTREFSEL
ANADETECT
HYST
RADIO — 2.4 GHz radio
Packet configuration
Address configuration
Data whitening
CRC
Radio states
Transmit sequence
Receive sequence
Received signal strength indicator (RSSI)
Interframe spacing (IFS)
Device address match
Bit counter
IEEE 802.15.4 operation
Packet structure
Operating frequencies
Energy detection (ED)
Clear channel assessment (CCA)
Cyclic redundancy check (CRC)
Transmit sequence
Receive sequence
Interframe spacing (IFS)
EasyDMA
Registers
TASKS_TXEN
TASKS_RXEN
TASKS_START
TASKS_STOP
TASKS_DISABLE
TASKS_RSSISTART
TASKS_BCSTART
TASKS_BCSTOP
TASKS_EDSTART
TASKS_EDSTOP
TASKS_CCASTART
TASKS_CCASTOP
TASKS_AUXDATADMASTART
TASKS_AUXDATADMASTOP
TASKS_PLLEN
TASKS_CSTONESSTART
TASKS_SOFTRESET
SUBSCRIBE_TXEN
SUBSCRIBE_RXEN
SUBSCRIBE_START
SUBSCRIBE_STOP
SUBSCRIBE_DISABLE
SUBSCRIBE_RSSISTART
SUBSCRIBE_BCSTART
SUBSCRIBE_BCSTOP
SUBSCRIBE_EDSTART
SUBSCRIBE_EDSTOP
SUBSCRIBE_CCASTART
SUBSCRIBE_CCASTOP
SUBSCRIBE_AUXDATADMASTART
SUBSCRIBE_AUXDATADMASTOP
SUBSCRIBE_PLLEN
SUBSCRIBE_CSTONESSTART
SUBSCRIBE_SOFTRESET
EVENTS_READY
EVENTS_TXREADY
EVENTS_RXREADY
EVENTS_ADDRESS
EVENTS_FRAMESTART
EVENTS_PAYLOAD
EVENTS_END
EVENTS_PHYEND
EVENTS_DISABLED
EVENTS_DEVMATCH
EVENTS_DEVMISS
EVENTS_CRCOK
EVENTS_CRCERROR
EVENTS_BCMATCH
EVENTS_EDEND
EVENTS_EDSTOPPED
EVENTS_CCAIDLE
EVENTS_CCABUSY
EVENTS_CCASTOPPED
EVENTS_RATEBOOST
EVENTS_MHRMATCH
EVENTS_SYNC
EVENTS_CTEPRESENT
EVENTS_PLLREADY
EVENTS_RXADDRESS
EVENTS_AUXDATADMAEND
EVENTS_CSTONESEND
PUBLISH_READY
PUBLISH_TXREADY
PUBLISH_RXREADY
PUBLISH_ADDRESS
PUBLISH_FRAMESTART
PUBLISH_PAYLOAD
PUBLISH_END
PUBLISH_PHYEND
PUBLISH_DISABLED
PUBLISH_DEVMATCH
PUBLISH_DEVMISS
PUBLISH_CRCOK
PUBLISH_CRCERROR
PUBLISH_BCMATCH
PUBLISH_EDEND
PUBLISH_EDSTOPPED
PUBLISH_CCAIDLE
PUBLISH_CCABUSY
PUBLISH_CCASTOPPED
PUBLISH_RATEBOOST
PUBLISH_MHRMATCH
PUBLISH_SYNC
PUBLISH_CTEPRESENT
PUBLISH_PLLREADY
PUBLISH_RXADDRESS
PUBLISH_AUXDATADMAEND
PUBLISH_CSTONESEND
SHORTS
INTENSET00
INTENSET01
INTENCLR00
INTENCLR01
INTENSET10
INTENSET11
INTENCLR10
INTENCLR11
MODE
PHYENDTXDELAY
STATE
EDCTRL
EDSAMPLE
CCACTRL
DATAWHITE
AUXDATA.CNF[n]
AUXDATADMA[n].ENABLE
AUXDATADMA[n].PTR
AUXDATADMA[n].MAXCNT
AUXDATADMA[n].AMOUNT
TIMING
FREQUENCY
TXPOWER
TIFS
RSSISAMPLE
RXGAIN.CONFIG
FREQFINETUNE
FECONFIG
CFO_STAT
DBCCORR
DFEMODE
DFESTATUS
DFECTRL1
DFECTRL2
SWITCHPATTERN
CLEARPATTERN
PSEL.DFEGPIO[n]
DFEPACKET
DFEPACKET.PTR
DFEPACKET.MAXCNT
DFEPACKET.AMOUNT
DFEPACKET.CURRENTAMOUNT
CRCSTATUS
RXMATCH
RXCRC
DAI
PDUSTAT
PCNF0
PCNF1
BASE0
BASE1
PREFIX0
PREFIX1
TXADDRESS
RXADDRESSES
CRCCNF
CRCPOLY
CRCINIT
DAB[n]
DAP[n]
DACNF
BCC
CTESTATUS
MHRMATCHCONF
MHRMATCHMASK
SFD
CTEINLINECONF
PACKETPTR
CSTONES.MODE
CSTONES.NUMSAMPLES
CSTONES.NEXTFREQUENCY
CSTONES.FAEPEER
CSTONES.PHASESHIFT
CSTONES.NUMSAMPLESCOEFF
CSTONES.PCT16
CSTONES.MAGPHASEMEAN
CSTONES.IQRAWMEAN
CSTONES.MAGSTD
CSTONES.FFOEST
CSTONES.DOWNSAMPLE
CSTONES.FREQOFFSET
RTT.CONFIG
RTT.SEGMENT01
RTT.SEGMENT23
RTT.SEGMENT45
RTT.SEGMENT67
SAADC — Successive approximation analog-to-digital converter
Shared resources
Overview
Digital output
Analog inputs and channels
Operation modes
One-shot mode
Continuous mode
Improving sampling accuracy
Scan mode
High-speed channel
EasyDMA
Reference
Acquisition time
Limits event monitoring
Registers
TASKS_START
TASKS_SAMPLE
TASKS_STOP
TASKS_CALIBRATEOFFSET
SUBSCRIBE_START
SUBSCRIBE_SAMPLE
SUBSCRIBE_STOP
SUBSCRIBE_CALIBRATEOFFSET
EVENTS_STARTED
EVENTS_END
EVENTS_DONE
EVENTS_RESULTDONE
EVENTS_CALIBRATEDONE
EVENTS_STOPPED
EVENTS_CH[n]
EVENTS_CH[n].LIMITH
EVENTS_CH[n].LIMITL
PUBLISH_STARTED
PUBLISH_END
PUBLISH_DONE
PUBLISH_RESULTDONE
PUBLISH_CALIBRATEDONE
PUBLISH_STOPPED
PUBLISH_CH[n]
PUBLISH_CH[n].LIMITH
PUBLISH_CH[n].LIMITL
INTEN
INTENSET
INTENCLR
STATUS
ENABLE
CH[n].PSELP
CH[n].PSELN
CH[n].CONFIG
CH[n].LIMIT
BURST
RESOLUTION
OVERSAMPLE
SAMPLERATE
RESULT
RESULT.PTR
RESULT.MAXCNT
RESULT.AMOUNT
RESULT.CURRENTAMOUNT
SPIM — Serial peripheral interface controller with EasyDMA
SPIM transaction sequence
D/CX functionality
Chip select hardware control
Pin configuration
Shared resources
EasyDMA
Low power
Registers
TASKS_START
TASKS_STOP
TASKS_SUSPEND
TASKS_RESUME
TASKS_DMA
TASKS_DMA.RX
TASKS_DMA.RX.ENABLEMATCH[n]
TASKS_DMA.RX.DISABLEMATCH[n]
SUBSCRIBE_START
SUBSCRIBE_STOP
SUBSCRIBE_SUSPEND
SUBSCRIBE_RESUME
SUBSCRIBE_DMA
SUBSCRIBE_DMA.RX
SUBSCRIBE_DMA.RX.ENABLEMATCH[n]
SUBSCRIBE_DMA.RX.DISABLEMATCH[n]
EVENTS_STARTED
EVENTS_STOPPED
EVENTS_END
EVENTS_DMA
EVENTS_DMA.RX
EVENTS_DMA.RX.END
EVENTS_DMA.RX.READY
EVENTS_DMA.RX.BUSERROR
EVENTS_DMA.RX.MATCH[n]
EVENTS_DMA.TX
EVENTS_DMA.TX.END
EVENTS_DMA.TX.READY
EVENTS_DMA.TX.BUSERROR
PUBLISH_STARTED
PUBLISH_STOPPED
PUBLISH_END
PUBLISH_DMA
PUBLISH_DMA.RX
PUBLISH_DMA.RX.END
PUBLISH_DMA.RX.READY
PUBLISH_DMA.RX.BUSERROR
PUBLISH_DMA.RX.MATCH[n]
PUBLISH_DMA.TX
PUBLISH_DMA.TX.END
PUBLISH_DMA.TX.READY
PUBLISH_DMA.TX.BUSERROR
SHORTS
INTENSET
INTENCLR
ENABLE
PRESCALER
CONFIG
IFTIMING.RXDELAY
IFTIMING.CSNDUR
DCXCNT
CSNPOL
ORC
PSEL.SCK
PSEL.MOSI
PSEL.MISO
PSEL.DCX
PSEL.CSN
DMA.RX.PTR
DMA.RX.MAXCNT
DMA.RX.AMOUNT
DMA.RX.LIST
DMA.RX.TERMINATEONBUSERROR
DMA.RX.BUSERRORADDRESS
DMA.RX.MATCH
DMA.RX.MATCH.CONFIG
DMA.RX.MATCH.CANDIDATE[n]
DMA.TX.PTR
DMA.TX.MAXCNT
DMA.TX.AMOUNT
DMA.TX.LIST
DMA.TX.TERMINATEONBUSERROR
DMA.TX.BUSERRORADDRESS
SPIS — Serial peripheral interface target with EasyDMA
SPI modes
Shared resources
EasyDMA
SPIS operation
Semaphore operation
Pin configuration
Registers
TASKS_ACQUIRE
TASKS_RELEASE
TASKS_DMA
TASKS_DMA.RX
TASKS_DMA.RX.ENABLEMATCH[n]
TASKS_DMA.RX.DISABLEMATCH[n]
SUBSCRIBE_ACQUIRE
SUBSCRIBE_RELEASE
SUBSCRIBE_DMA
SUBSCRIBE_DMA.RX
SUBSCRIBE_DMA.RX.ENABLEMATCH[n]
SUBSCRIBE_DMA.RX.DISABLEMATCH[n]
EVENTS_END
EVENTS_ACQUIRED
EVENTS_DMA
EVENTS_DMA.RX
EVENTS_DMA.RX.END
EVENTS_DMA.RX.READY
EVENTS_DMA.RX.BUSERROR
EVENTS_DMA.RX.MATCH[n]
EVENTS_DMA.TX
EVENTS_DMA.TX.END
EVENTS_DMA.TX.READY
EVENTS_DMA.TX.BUSERROR
PUBLISH_END
PUBLISH_ACQUIRED
PUBLISH_DMA
PUBLISH_DMA.RX
PUBLISH_DMA.RX.END
PUBLISH_DMA.RX.READY
PUBLISH_DMA.RX.BUSERROR
PUBLISH_DMA.RX.MATCH[n]
PUBLISH_DMA.TX
PUBLISH_DMA.TX.END
PUBLISH_DMA.TX.READY
PUBLISH_DMA.TX.BUSERROR
SHORTS
INTENSET
INTENCLR
SEMSTAT
STATUS
ENABLE
CONFIG
DEF
ORC
PSEL.SCK
PSEL.MISO
PSEL.MOSI
PSEL.CSN
DMA.RX.PTR
DMA.RX.MAXCNT
DMA.RX.AMOUNT
DMA.RX.TERMINATEONBUSERROR
DMA.RX.BUSERRORADDRESS
DMA.RX.MATCH
DMA.RX.MATCH.CONFIG
DMA.RX.MATCH.CANDIDATE[n]
DMA.TX.PTR
DMA.TX.MAXCNT
DMA.TX.AMOUNT
DMA.TX.TERMINATEONBUSERROR
DMA.TX.BUSERRORADDRESS
TEMP — Temperature sensor
Operation
Registers
TASKS_START
TASKS_STOP
SUBSCRIBE_START
SUBSCRIBE_STOP
EVENTS_DATARDY
PUBLISH_DATARDY
INTENSET
INTENCLR
TEMP
A0
A1
A2
A3
A4
A5
A6
B0
B1
B2
B3
B4
B5
B6
T0
T1
T2
T3
T4
T5
TIMER — Timer/counter
Capture
Compare
Task delays
Task priority
Registers
TASKS_START
TASKS_STOP
TASKS_COUNT
TASKS_CLEAR
TASKS_CAPTURE[n]
SUBSCRIBE_START
SUBSCRIBE_STOP
SUBSCRIBE_COUNT
SUBSCRIBE_CLEAR
SUBSCRIBE_CAPTURE[n]
EVENTS_COMPARE[n]
PUBLISH_COMPARE[n]
SHORTS
INTEN
INTENSET
INTENCLR
MODE
BITMODE
PRESCALER
CC[n]
ONESHOTEN[n]
TWIM — I2C compatible two-wire interface controller with EasyDMA
TWIM operation
Shared resources
EasyDMA
TWIM write sequence
TWIM read sequence
TWIM repeated start sequence
Low power
TWIM pin configuration
Pull-up resistor
Registers
TASKS_STOP
TASKS_SUSPEND
TASKS_RESUME
TASKS_DMA
TASKS_DMA.RX
TASKS_DMA.RX.START
TASKS_DMA.RX.STOP
TASKS_DMA.RX.ENABLEMATCH[n]
TASKS_DMA.RX.DISABLEMATCH[n]
TASKS_DMA.TX
TASKS_DMA.TX.START
TASKS_DMA.TX.STOP
SUBSCRIBE_STOP
SUBSCRIBE_SUSPEND
SUBSCRIBE_RESUME
SUBSCRIBE_DMA
SUBSCRIBE_DMA.RX
SUBSCRIBE_DMA.RX.START
SUBSCRIBE_DMA.RX.STOP
SUBSCRIBE_DMA.RX.ENABLEMATCH[n]
SUBSCRIBE_DMA.RX.DISABLEMATCH[n]
SUBSCRIBE_DMA.TX
SUBSCRIBE_DMA.TX.START
SUBSCRIBE_DMA.TX.STOP
EVENTS_STOPPED
EVENTS_ERROR
EVENTS_SUSPENDED
EVENTS_LASTRX
EVENTS_LASTTX
EVENTS_DMA
EVENTS_DMA.RX
EVENTS_DMA.RX.END
EVENTS_DMA.RX.READY
EVENTS_DMA.RX.BUSERROR
EVENTS_DMA.RX.MATCH[n]
EVENTS_DMA.TX
EVENTS_DMA.TX.END
EVENTS_DMA.TX.READY
EVENTS_DMA.TX.BUSERROR
PUBLISH_STOPPED
PUBLISH_ERROR
PUBLISH_SUSPENDED
PUBLISH_LASTRX
PUBLISH_LASTTX
PUBLISH_DMA
PUBLISH_DMA.RX
PUBLISH_DMA.RX.END
PUBLISH_DMA.RX.READY
PUBLISH_DMA.RX.BUSERROR
PUBLISH_DMA.RX.MATCH[n]
PUBLISH_DMA.TX
PUBLISH_DMA.TX.END
PUBLISH_DMA.TX.READY
PUBLISH_DMA.TX.BUSERROR
SHORTS
INTEN
INTENSET
INTENCLR
ERRORSRC
ENABLE
FREQUENCY
ADDRESS
PSEL.SCL
PSEL.SDA
DMA.RX.PTR
DMA.RX.MAXCNT
DMA.RX.AMOUNT
DMA.RX.TERMINATEONBUSERROR
DMA.RX.BUSERRORADDRESS
DMA.RX.MATCH
DMA.RX.MATCH.CONFIG
DMA.RX.MATCH.CANDIDATE[n]
DMA.TX.PTR
DMA.TX.MAXCNT
DMA.TX.AMOUNT
DMA.TX.TERMINATEONBUSERROR
DMA.TX.BUSERRORADDRESS
TWIS — I2C compatible two-wire interface target with EasyDMA
State machine
Shared resources
EasyDMA
Read command response
Write command response
TWI controller repeated start sequence
Terminate an ongoing TWI transaction
Low power
Target mode pin configuration
Registers
TASKS_STOP
TASKS_SUSPEND
TASKS_RESUME
TASKS_PREPARERX
TASKS_PREPARETX
TASKS_DMA
TASKS_DMA.RX
TASKS_DMA.RX.ENABLEMATCH[n]
TASKS_DMA.RX.DISABLEMATCH[n]
SUBSCRIBE_STOP
SUBSCRIBE_SUSPEND
SUBSCRIBE_RESUME
SUBSCRIBE_PREPARERX
SUBSCRIBE_PREPARETX
SUBSCRIBE_DMA
SUBSCRIBE_DMA.RX
SUBSCRIBE_DMA.RX.ENABLEMATCH[n]
SUBSCRIBE_DMA.RX.DISABLEMATCH[n]
EVENTS_STOPPED
EVENTS_ERROR
EVENTS_WRITE
EVENTS_READ
EVENTS_DMA
EVENTS_DMA.RX
EVENTS_DMA.RX.END
EVENTS_DMA.RX.READY
EVENTS_DMA.RX.BUSERROR
EVENTS_DMA.RX.MATCH[n]
EVENTS_DMA.TX
EVENTS_DMA.TX.END
EVENTS_DMA.TX.READY
EVENTS_DMA.TX.BUSERROR
PUBLISH_STOPPED
PUBLISH_ERROR
PUBLISH_WRITE
PUBLISH_READ
PUBLISH_DMA
PUBLISH_DMA.RX
PUBLISH_DMA.RX.END
PUBLISH_DMA.RX.READY
PUBLISH_DMA.RX.BUSERROR
PUBLISH_DMA.RX.MATCH[n]
PUBLISH_DMA.TX
PUBLISH_DMA.TX.END
PUBLISH_DMA.TX.READY
PUBLISH_DMA.TX.BUSERROR
SHORTS
INTEN
INTENSET
INTENCLR
ERRORSRC
MATCH
ENABLE
ADDRESS[n]
CONFIG
ORC
PSEL.SCL
PSEL.SDA
DMA.RX.PTR
DMA.RX.MAXCNT
DMA.RX.AMOUNT
DMA.RX.TERMINATEONBUSERROR
DMA.RX.BUSERRORADDRESS
DMA.RX.MATCH
DMA.RX.MATCH.CONFIG
DMA.RX.MATCH.CANDIDATE[n]
DMA.TX.PTR
DMA.TX.MAXCNT
DMA.TX.AMOUNT
DMA.TX.TERMINATEONBUSERROR
DMA.TX.BUSERRORADDRESS
UARTE — Universal asynchronous receiver/transmitter with EasyDMA
Baudrate
EasyDMA
Transmission
Reception
Data frame size
Frame timeout interrupt
Error conditions
Using the UARTE without flow control
Parity and stop bit configuration
Compare match filter
Low power
Pin configuration
Registers
TASKS_FLUSHRX
TASKS_DMA
TASKS_DMA.RX
TASKS_DMA.RX.START
TASKS_DMA.RX.STOP
TASKS_DMA.RX.ENABLEMATCH[n]
TASKS_DMA.RX.DISABLEMATCH[n]
TASKS_DMA.TX
TASKS_DMA.TX.START
TASKS_DMA.TX.STOP
SUBSCRIBE_FLUSHRX
SUBSCRIBE_DMA
SUBSCRIBE_DMA.RX
SUBSCRIBE_DMA.RX.START
SUBSCRIBE_DMA.RX.STOP
SUBSCRIBE_DMA.RX.ENABLEMATCH[n]
SUBSCRIBE_DMA.RX.DISABLEMATCH[n]
SUBSCRIBE_DMA.TX
SUBSCRIBE_DMA.TX.START
SUBSCRIBE_DMA.TX.STOP
EVENTS_CTS
EVENTS_NCTS
EVENTS_TXDRDY
EVENTS_RXDRDY
EVENTS_ERROR
EVENTS_RXTO
EVENTS_TXSTOPPED
EVENTS_DMA
EVENTS_DMA.RX
EVENTS_DMA.RX.END
EVENTS_DMA.RX.READY
EVENTS_DMA.RX.BUSERROR
EVENTS_DMA.RX.MATCH[n]
EVENTS_DMA.TX
EVENTS_DMA.TX.END
EVENTS_DMA.TX.READY
EVENTS_DMA.TX.BUSERROR
EVENTS_FRAMETIMEOUT
PUBLISH_CTS
PUBLISH_NCTS
PUBLISH_TXDRDY
PUBLISH_RXDRDY
PUBLISH_ERROR
PUBLISH_RXTO
PUBLISH_TXSTOPPED
PUBLISH_DMA
PUBLISH_DMA.RX
PUBLISH_DMA.RX.END
PUBLISH_DMA.RX.READY
PUBLISH_DMA.RX.BUSERROR
PUBLISH_DMA.RX.MATCH[n]
PUBLISH_DMA.TX
PUBLISH_DMA.TX.END
PUBLISH_DMA.TX.READY
PUBLISH_DMA.TX.BUSERROR
PUBLISH_FRAMETIMEOUT
SHORTS
INTEN
INTENSET
INTENCLR
ERRORSRC
ENABLE
BAUDRATE
CONFIG
ADDRESS
FRAMETIMEOUT
PSEL.TXD
PSEL.CTS
PSEL.RXD
PSEL.RTS
DMA.RX.PTR
DMA.RX.MAXCNT
DMA.RX.AMOUNT
DMA.RX.TERMINATEONBUSERROR
DMA.RX.BUSERRORADDRESS
DMA.RX.MATCH
DMA.RX.MATCH.CONFIG
DMA.RX.MATCH.CANDIDATE[n]
DMA.TX.PTR
DMA.TX.MAXCNT
DMA.TX.AMOUNT
DMA.TX.TERMINATEONBUSERROR
DMA.TX.BUSERRORADDRESS
VPR — RISC-V CPU
Registers
TASKS_TRIGGER[n]
SUBSCRIBE_TRIGGER[n]
EVENTS_TRIGGERED[n]
PUBLISH_TRIGGERED[n]
INTEN
INTENSET
INTENCLR
INTPEND
DEBUGIF.DATA0
DEBUGIF.DATA1
DEBUGIF.DMCONTROL
DEBUGIF.DMSTATUS
DEBUGIF.HARTINFO
DEBUGIF.HALTSUM1
DEBUGIF.HAWINDOWSEL
DEBUGIF.HAWINDOW
DEBUGIF.ABSTRACTCS
DEBUGIF.ABSTRACTCMD
DEBUGIF.ABSTRACTAUTO
DEBUGIF.CONFSTRPTR[n]
DEBUGIF.NEXTDM
DEBUGIF.PROGBUF[n]
DEBUGIF.AUTHDATA
DEBUGIF.HALTSUM2
DEBUGIF.HALTSUM3
DEBUGIF.SBADDRESS3
DEBUGIF.SBCS
DEBUGIF.SBADDRESS0
DEBUGIF.SBADDRESS1
DEBUGIF.SBADDRESS2
DEBUGIF.SBDATA0
DEBUGIF.SBDATA1
DEBUGIF.SBDATA2
DEBUGIF.SBDATA3
DEBUGIF.HALTSUM0
CPURUN
VPRSTATUS
INITPC
Registers
CLIC.CLICCFG
CLIC.CLICINFO
CLIC.CLICINT[n]
Registers
MSTATUS
MISA
MTVEC
MTVT
MCOUNTINHIBIT
MSCRATCH
MEPC
MCAUSE
MTVAL
MINTSTATUS
MINTTHRESH
MCLICBASE
TSELECT
TDATA1
TDATA2
TDATA3
TINFO
TCONTROL
DCSR
DPC
MCYCLE
MINSTRET
MCYCLEH
MINSTRETH
UCYCLE
UINSTRET
UCYCLEH
UINSTRETH
MVENDORID
MARCHID
MIMPID
MHARTID
NORDIC.VPRNORDICCTRL
NORDIC.VPRNORDICSLEEPCTRL
NORDIC.VPRNORDICFEATURESDISABLE
NORDIC.VIOPINS
NORDIC.EXTPARAMS
NORDIC.CACHE.AXCACHE
NORDIC.CACHE.CTRL
NORDIC.CACHE.CFG
NORDIC.CACHE.DATATAGADDR
NORDIC.CACHE.DATABASEADDR
NORDIC.RTPERIPHCTRL
NORDIC.RTPERIPHSTATUS
NORDIC.CNTMODE0
NORDIC.CNTMODE1
NORDIC.CNT
NORDIC.CNTTOP
NORDIC.CNTADD
NORDIC.CNT0
NORDIC.CNTADD0
NORDIC.CNT1
NORDIC.CNTADD1
NORDIC.WAIT0
NORDIC.WAIT1
NORDIC.WAIT
NORDIC.TASKS
NORDIC.SUBSCRIBE
NORDIC.EVENTS
NORDIC.PUBLISH
NORDIC.INTEN
NORDIC.EVENTSB
NORDIC.EVENTSBS
NORDIC.OUT
NORDIC.DIR
NORDIC.IN
NORDIC.INMODE
NORDIC.OUTB
NORDIC.DIRB
NORDIC.DIROUT
NORDIC.DIROUTB
NORDIC.OUTBRB
NORDIC.OUTBRW
NORDIC.INBRB
NORDIC.SHIFTCTRLB
NORDIC.SHIFTCNTIN
NORDIC.SHIFTCNTOUT
NORDIC.SHIFTCNTB
NORDIC.OUTTGL
NORDIC.DIRTGL
NORDIC.OUTBTGL
NORDIC.DIRBTGL
NORDIC.DIROUTTGL
NORDIC.DIROUTBTGL
NORDIC.OUTUBTGL
NORDIC.OUTBS
NORDIC.DIRBS
NORDIC.DIROUTBS
NORDIC.OUTUBS
NORDIC.OUTBD
NORDIC.OUTBDTGL
NORDIC.OUTBDS
NORDIC.OUTMODE
NORDIC.OUTMODEB
NORDIC.INMODEB
NORDIC.INB
NORDIC.OUTUB
NORDIC.SHIFTCNTCOMP
NORDIC.WAITEVENT
NORDIC.WAITINPUT
NORDIC.RTPINTEN
NORDIC.OUTUBTRIG
WDT — Watchdog timer
Reload criteria
Temporarily pausing the watchdog
Watchdog reset
Stopping the watchdog
Registers
TASKS_START
TASKS_STOP
SUBSCRIBE_START
SUBSCRIBE_STOP
EVENTS_TIMEOUT
EVENTS_STOPPED
PUBLISH_TIMEOUT
PUBLISH_STOPPED
INTENSET
INTENCLR
NMIENSET
NMIENCLR
RUNSTATUS
REQSTATUS
CRV
RREN
CONFIG
TSEN
RR[n]
Debug and trace
Debug access port
Debug access port registers
TARGETID
DLPIDR
Access port protection
Debug Interface mode
Real-time debug
Multidrop serial wire debug
Trace
Enabling the trace port
CTRL-AP — Control access port
Reset request
Erase all
Erase protection
Mailbox interface
Device information
Debugger registers
Debug side registers
RESET
ERASEALL
ERASEALLSTATUS
ERASEPROTECT.STATUS
ERASEPROTECT.DISABLE
APPROTECT.STATUS
MAILBOX.TXDATA
MAILBOX.TXSTATUS
MAILBOX.RXDATA
MAILBOX.RXSTATUS
INFO.PARTNO
INFO.HWREVISION
IDR
Peripheral registers
CPU side registers
EVENTS_RXREADY
EVENTS_TXDONE
INTEN
INTENSET
INTENCLR
INTPEND
MAILBOX.RXDATA
MAILBOX.RXSTATUS
MAILBOX.TXDATA
MAILBOX.TXSTATUS
ERASEPROTECT.LOCK
ERASEPROTECT.DISABLE
RESET
TAD — Trace and debug control
Registers
SYSPWRUPREQ
DBGPWRUPREQ
ENABLE
TRACEPORTSPEED (Retained)
ETM — Embedded trace macrocell
Registers
TRCPRGCTLR
TRCPROCSELR
TRCSTATR
TRCCONFIGR
TRCEVENTCTL0R
TRCEVENTCTL1R
TRCSTALLCTLR
TRCTSCTLR
TRCSYNCPR
TRCCCCTLR
TRCBBCTLR
TRCTRACEIDR
TRCQCTLR
TRCVICTLR
TRCVIIECTLR
TRCVISSCTLR
TRCVIPCSSCTLR
TRCVDCTLR
TRCVDSACCTLR
TRCVDARCCTLR
TRCSEQEVR[n]
TRCSEQRSTEVR
TRCSEQSTR
TRCEXTINSELR
TRCCNTRLDVR[n]
TRCCNTCTLR[n]
TRCCNTVR[n]
TRCRSCTLR[n]
TRCSSCCR0
TRCSSCSR0
TRCSSPCICR0
TRCPDCR
TRCPDSR
TRCITATBIDR
TRCITIATBINR
TRCITIATBOUTR
TRCITCTRL
TRCCLAIMSET
TRCCLAIMCLR
TRCAUTHSTATUS
TRCDEVARCH
TRCDEVTYPE
TRCPIDR[n]
TRCCIDR[n]
TPIU — Trace port interface unit
Registers
Hardware and layout
Pin assignments
Dedicated pins
Clock pins
QFN48 (QFAA) package pin assignments
CSP29 (CAAA) package pin assignments
Mechanical specifications
QFN48 (QFAA) package
CSP29 (CAAA) package
Reference circuitry
Circuit configuration 1 for CSP29 (CAAA)
Circuit configuration 1 for QFN48 (QFAA)
PCB layout example
Reflow conditions
Electrical specifications
CLOCK Electrical specification
High frequency clock source (HFCLK)
32.768 kHz clock source (LFCLK)
CPU Electrical specification
CPU performance
CPU wakeup times
GPIO Electrical specification
GPIO Electrical Specification
OSCILLATORS Electrical specification
32 MHz crystal oscillator (HFXO)
32.768 kHz crystal oscillator (LFXO)
PPI Electrical specification
Typical PPI latencies
REGULATORS Electrical specification
Recommended operating conditions
Power-fail comparator
RRAMC Electrical specification
RRAM programming
SPIM Electrical specification
Timing specifications
Timing specifications for GPIO port P0 using Standard drive strength
Timing specifications for GPIO port P0 using High drive strength
Timing specifications for GPIO port P1 using Standard drive strength
Timing specifications for GPIO port P1 using High drive strength
SPIS Electrical specification
SPIS slave interface electrical specifications
Serial Peripheral Interface Slave (SPIS) timing specifications
Timing specifications for GPIO port P0 using Standard drive strength
Timing specifications for GPIO port P0 using High drive strength
Timing specifications for GPIO port P1 using Standard drive strength
Timing specifications for GPIO port P1 using High drive strength
SWDP Electrical specification
SW-DP
Trace port
TWIM Electrical specification
TWIM interface electrical specifications
Two Wire Interface Master (TWIM) timing specifications
TWIS Electrical specification
TWIS slave timing specifications
UARTE Electrical specification
UARTE electrical specification
WDT Electrical specification
Watchdog Timer Electrical Specification
Current consumption
Conditions
CURRENT Electrical specification
Sleep
CPU running
RADIO transmitting/receiving
Recommended operating conditions
CSP light sensitivity
Absolute maximum ratings
Legal notices

32 MHz oscillator control

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