Serial Peripheral Interface Slave (SPIS) timing specifications

nRF54LV10A Preliminary Datasheet
Symbol Description Min. Typ. Max. Units
tSPIS,CSCKIN

SCK input period

 125 ns
tSPIS,RFSCKIN

SCK input rise/fall time

 30 ns
tSPIS,WHSCKIN

SCK input high time

 30 ns
tSPIS,WLSCKIN

SCK input low time

 30 ns
tSPIS,SUCSN

CSN to CLK setup time

 10004 ns
tSPIS,HCSN

CLK to CSN hold time

 1000 ns
tSPIS,ASA

CSN to SDO driven

 70 ns
tSPIS,ASO

CSN to SDO valid5

 1000 ns
tSPIS,DISSO

CSN to SDO disabled5

 70 ns
tSPIS,CWH

CSN inactive time

 300 ns
Figure 2. SPIS timing diagram, CPHA = 0
SPIS timing diagram
Figure 3. SPIS timing diagram, CPHA = 1
SPIS timing diagram
Figure 4. Common SPIM and SPIS timing diagram
Common SPIM and SPIS timing diagram
4 Excluding any start-up delay for the high frequency clock in low power mode.
5 At 25pF load, including GPIO capacitance, see GPIO spec.