To prevent leakage during nRF9151 power-on, apply power to VDD and ENABLE before VDD_GPIO. For nRF9151 power-down, turn off VDD_GPIO before VDD and ENABLE.
The following recommendations apply to the ENABLE, VDD, and VDD_GPIO pins.
- VDD_GPIO should be applied at least 6 ms after ENABLE and VDD have been supplied.
- VDD_GPIO should be removed before removing ENABLE or VDD.
- If ENABLE and VDD are supplied and VDD_GPIO is grounded, extra current consumption is generated on VDD. If possible, keep VDD_GPIO floating.
- If the ENABLE pin is low, VDD_GPIO should also be low.
The following figure shows the recommended power-on cycle for the nRF9151.
After ENABLE and VDD are applied, nRF9151 must complete a hardware boot before VDD_GPIO is applied. If VDD_GPIO is applied before the nRF9151 hardware boot completes, the GPIO states are undefined.
ENABLE can be set high after VDD is high. In this case, nRF9151 is enabled when ENABLE > 0.89xVDD. Use a delay of more than 6 ms for VDD_GPIO. The same delay is used when VDD and ENABLE are applied at the same time.
The following figure shows the recommended power-off cycle for the nRF9151.
Power down VDD_GPIO before you remove VDD or set ENABLE to low.
If VDD_GPIO voltage is present when ENABLE or VDD is low, the GPIO states are undefined. If the end application can tolerate undefined GPIO states, you can remove VDD_GPIO after VDD or ENABLE is set to low.
The following table shows a summary of the powering states.
| ENABLE | VDD | VDD_GPIO | Comment |
|---|---|---|---|
| High | High | High | No leakage |
| High | High | Low | High (mA) leakage to VDD |
| High | High | Float | No leakage |
| High | Low | Low | High (mA) leakage to ENABLE |
| High | Low/float | High | High (mA) leakage to ENABLE |
| Low | High | High | High (mA) leakage to VDD_GPIO |
| Low | High | Low/float | No leakage |
| Low | Low/float | Low/float | No leakage |
| Low | Low/float | High | High (mA) leakage to VDD_GPIO |