ENABLE (pin 10) is a high-impedance control pin for the nRF9151-internal power management unit (PMU). It is used to enable and disable nRF9151.
A logic high (≥ 0.89xVDD) enables nRF9151. The start delay for Serial Wire Debug (SWD) access is in the range of 100–500 ms from the time the ENABLE pin is pulled high. If nRF9151 has no programmed firmware, wait for about 100 ms. If application firmware is programmed and the modem starts in normal mode, SWD should be delayed until the firmware has started. Typically, this takes about 500 ms.
A logic low (≤ 0.18xVDD) disables nRF9151 and brings it into extremely low current consumption. Keep the ENABLE pin low for a minimum of 1 s.
In products where nRF9151 is always enabled, the ENABLE pin can be connected to VDD (pin 14) on the application board with a series resistor. The series resistor minimizes digital noise coupling between the VDD and ENABLE pins. It is recommended to add a decoupling capacitor to the ENABLE pin. If ENABLE is connected to VDD, a shared capacitor can be used for the ENABLE and VDD pins, if the VDD decoupling capacitor is located close to these pins.
PCB layout design
When designing the PCB layout, consider the following recommendations for the ENABLE pin:
- Place R1 close to the ENABLE pin.
- If ENABLE is directly connected to VDD, it can use a shared decoupling capacitor with VDD if the decoupling capacitor and ENABLE are located close to each other.
- If ENABLE is not directly connected to VDD, a dedicated decoupling capacitor is recommended to be added to the ENABLE pin.
- Because ENABLE can carry noise from internal and external regulators and the power source, it is not recommended to be routed parallel to sensitive routings, such as RF.
- Avoid routing the ENABLE signal unshielded on the top and bottom metal layers of the PCB as this risks radiated noise that can deteriorate radiated Global Navigation Satellite System (GNSS) and Long-Term Evolution (LTE) sensitivity.