VDD_GPIO

nRF9151 Hardware Design Guidelines

VDD_GPIO (pin 65) is the supply for application General-Purpose Input/Output (GPIO)s P0.00–P0.31 and the COEX interface (pins 52–54) that is provided externally.

The operating voltage of VDD_GPIO ranges from 1.7 V to 3.6 V and is independent of the VDD supply.

The current consumption of VDD_GPIO is mostly controlled by the end product design. This is because VDD_GPIO supplies the application GPIOs which are controlled by the application software provided by the system integrator. If the GPIOs are not significantly stressed in the device, VDD_GPIO can have a simple power supply strategy. However, if the end product has high momentary current draw from the GPIOs, VDD_GPIO's capability must be designed to comply with it.

In the worst case, the momentary concurrent current consumption of all GPIOs should not peak higher than approximately 100 mA. Regardless of the VDD_GPIO's supply capability, it is not recommended to have long periods of high concurrent consumption because it increases the risk of reducing the device's lifetime.

For VDD_GPIO, the minimum recommendation is the low ESR supply capacitor C6. Filtering for high-frequency components can be improved by adding supply capacitor C5. The components' electrical values can vary depending on the application.

The following recommendations apply to the VDD_GPIO pin:

  • VDD_GPIO should be applied at least 6 ms after ENABLE and VDD have been supplied.
  • VDD_GPIO should be removed before removing ENABLE or VDD.
  • If ENABLE and VDD are supplied and VDD_GPIO is grounded, extra current consumption is generated on VDD. If possible, keep VDD_GPIO floating.
  • If the ENABLE pin is low, VDD_GPIO should also be low.
If VDD_GPIO is applied before the nRF9151 hardware boot is completed, the GPIO states are undefined. This can cause short high-state pulses to the GPIOs. If the end application can tolerate undefined GPIO states, VDD_GPIO can be applied without a 6 ms delay. For more information, see ENABLE sequence.
Note: nRF9151's internal ESD protection diodes in the GPIO pins connect to the VDD_GPIO supply net. If the voltage on the GPIO pin is higher than the VDD_GPIO supply, it can cause leakage from the GPIO pins towards the VDD_GPIO net.

PCB layout design

When designing the PCB layout, consider the following recommendations for the VDD_GPIO pin:

  • Place capacitors C5 and C6 close to the VDD_GPIO pin for good power delivery.
  • Use a track that is wide enough (DCR < 0.1 Ω) for VDD_GPIO routing to minimize voltage drops and unwanted power consumption due to routing losses under high current conditions.
  • Connect capacitors to the same ground plane as nRF9151 using low impedance ground connections.
  • Avoid supply routings close or adjacent to sensitive routings, such as RF.
  • Use shielded PCB layers for routings whenever possible to minimize radiated noise.
  • Use plenty of ground vias along supply routings to minimize unwanted voltage differences in the application PCB's metal layers.
  • A series solder bridge is recommended in the VDD_GPIO routing for current consumption measurements or other diagnostic purposes.