The application General-Purpose Input/Output (GPIO) pins (P0.00–P0.31) are used for interfacing and communicating with application peripherals like sensors, Integrated Circuit (IC)s, external memories, buttons, and LEDs.
The GPIOs have the following user-configurable features:
- Configurable output drive strength
- Internal pull-up and pull-down resistors
- Wake-up from high-level or low-level triggers on all pins
- Trigger interrupt on state changes on any pin
- All pins can be used by the Programmable Peripheral Interconnect (PPI) task system
- One or more GPIO output can be controlled through PPI and GPIOTE channels
- All pins can be individually mapped to interface blocks for layout's flexibility
- GPIO state changes captured on the SENSE signal can be stored by the LATCH register
- Support for secure and non-secure attributes for pins in conjunction with the system protection unit
The GPIOs have two software-configurable drive modes, which are standard drive mode and high drive mode. For more information, see GPIO Electrical Specification in nRF9151 Product Specification.
Standard drive is recommended because lower current results in better EMI performance and interoperability with other application board peripherals. With standard drive, the end product typically performs better in areas like LTE radiated spurious emissions and LTE receiver radiated sensitivity than with high drive.
GPIOs are powered from VDD_GPIO. They have the same voltage level as VDD_GPIO and any unwanted noise or spurious that VDD_GPIO might contain. Therefore, it is important to have proper noise filtering in VDD_GPIO (pin 65). It is also important for each individual GPIO pin to meet the filtering requirements specified for the peripherals connected to them. To avoid digital noise generated by the GPIOs, fast transients should be avoided. It is recommended to use the slowest possible rise times that the peripherals connected to the GPIOs allow.
To reduce transient currents, series resistors or ferrite beads can be used on the GPIO lines. For GPIOs, resistors in the range of 100 Ω to 1 kΩ can be considered as they are low current digital controls. Optimal resistor values depend mainly on the connected peripheral drive currents and communication speed or other application-level requirements. In addition to the series resistor, bypass capacitors in the range of a few pF can be considered. They can help to reduce RF coupling to the GPIO lines. Unused GPIOs can be left electrically unconnected, but it is recommended to solder them to the application board for improved thermal and mechanical performance.
When ENABLE and VDD are high, the GPIOs are set to the reset state, which is high impedance. The GPIOs stays in the high impedance state until the application firmware (customer software) changes the state. If VDD_GPIO is off, any voltage supplied to GPIO pins will leak to the VDD_GPIO net through the ESD diodes when the voltage exceeds 0.6 V.
For more information on GPIO feature support, see GPIO - General purpose input/output in nRF9151 Product Specification.
PCB layout design
When designing the PCB layout, consider the following recommendations for the GPIO pins:
- Place filtering series resistors close to the respective GPIO pins.
- Place capacitors close to the origin of noise and ground them to the same ground plane as GND on nRF9151.
- Avoid parallel routing of GPIOs close to sensitive RF routes due to the risk of noise coupling from the GPIO to the RF routing.
- Avoid parallel routing of GPIOs close to supply or RF routes due to the risk of noise coupling from other routes to the GPIO routes.
- Use shielded PCB layers for GPIO routings whenever possible to minimize radiated noise.
- Follow the instructions in the peripheral datasheets.