MIPI RF front-end

nRF9151 Hardware Design Guidelines

MIPI RF Front-End Control Interface (RFFE) is a dedicated RF front-end component control interface.

It consists of VIO (pin 29), SCLK (pin 28), and SDATA (pin 27). VIO is a 1.8 V output supply for the MIPI controller, SCLK is the clock for the controller, and SDATA is for the control data. The maximum output current for VIO is 10 mA. The RFFE interface is aligned with the Long-Term Evolution (LTE) protocol, which enables LTE protocol synchronous control for nRF9151-external components, such as an antenna tuner.

nRF9151 supports RFFE v1.1 with the following exceptions:

  • SCLK is fixed rate at 19.2 MHz.
  • One or two RFFE components are supported at a time depending on the modem firmware version.
  • The VIO voltage can be high at any time when nRF9151 is active, not only when external RFFE components are used.
  • The capacitive load of SCLK and SDATA must not exceed 15 pF on the application board.

VIO is ON only when RF is awake. Therefore, VIO is OFF during DRX, eDRX, and PSM sleep.

After VDD and ENABLE pins go high, SCLK and SDATA reset to a pull-down state.

For noise filtering and diagnostic purposes, it is recommended to add series resistors in the range of 1 kΩ to SCLK and SDATA. In addition to the series resistor, bypass capacitors in the range of a few pF can be considered. They can help to reduce RF coupling to the RFFE lines. Additional capacitance increases the RFFE load and potentially deteriorates signal integrity. By default, it is not recommended to assemble bypass capacitors.

The nRF9151-internal MIPI RFFE USID is 15 and thus not available for use by any external MIPI RFFE component.

In the Non-Terrestrial Network (NTN) firmware (mfw_nrf9151-ntn), nRF9151 supports two external MIPI RFFE devices. For more information, see nRF91x1 NTN AT Commands.

Note: In CFUN=1 mode there are short periodic sleeps during which VIO is OFF. VIO ON and VIO OFF are controlled automatically. At wakeup, VIO and MIPI RFFE states are automatically restored by nRF9151.

VIO should be assumed to be high when the LTE modem is active. Even though VIO is tied to RF-domain power state, it is safe to assume VIO to be high for short periods outside of RF activity. Therefore, an external RFFE component should not have excessive current leakage at VIO in any conditions. Typically, VIO consumption or leakage in RFFE components is very low, but it is recommended to be verified from the component datasheet. External RFFE components must withstand a situation where VIO is high, but external RFFE component supply is low. Typically, this is acceptable, but some RFFE components can be more sensitive than others.

The combined load of PCB routing, input load of the RFFE component controller, and parasitic load from the application shall not exceed 15 pF at nRF9151's SCLK or SDATA pins. Typically, this load equals narrow transmission line length of ≤ 10 cm on the application board, but depends on the actual PCB design.

PCB layout design

When designing the PCB layout, consider the following recommendations for the MIPI RFFE interface:

  • Parasitic capacitance in routing must not exceed 15 pF at SCLK or SDATA.
  • If additional filtering is needed, place bypass filtering capacitors close to the component that MIPI RFFE is connected to and where the noise originates from, for example, the antenna tuner.
  • Avoid adjacent routings of SCLK and SDATA to noisy routings, such as RF or supply.
  • Use shielded PCB layers for RFFE routings whenever possible to minimize radiated coupling.
  • Follow the instructions of the RFFE peripheral datasheets.