The GPIO peripheral implements two pins, GPIO0 and GPIO1. Both pins can be individually configured in the CONFIG[n], USAGE[n], and OUTPUT[n] registers.

Note: GPIO pins cannot be used while in Hibernate, Hibernate_PT, or Ship mode.

General purpose input

GPIO can be used as a general purpose input to monitor the input logic level. For a pin to function as a GPIO, select GPIO in register USAGE[n]. Input buffer enable, debounce, pull-down, and pull-up are set in the CONFIG[n] register. Pin state can be read in the READ register.

GPIO can also be used as an input to trigger an event using INTEN_GPIO_SET to enable events. Set bit GPIO[n]RISE to generate an event on the rising edge. To generate an event on a falling edge, set bit GPIO[n]FALL. The events are visible in register EVENTS_GPIO_SET.

Control input

For a pin to function as a control input, first select GPIO in USAGE[n], then configure the pin in CONFIG[n].

The following components can be controlled through GPIO once enabled in the corresponding register.

Output

For a pin to function as an output, select GPIO in the USAGE[n] register. Use the CONFIG[n] register to enable the output buffer and configure the settings. OUTPUT[n] drives the pin to the desired state.

Note: In case of a power cycle, the GPIOs are reset and return to their default state (input, pull-down) once delay tPWRDN has completely elapsed. The GPIOs are internally supplied by VINT. In case a GPIO pin is configured as a push-pull (a.k.a. CMOS) output and connected to the host MCU, backfeeding of power to host's supply rail (VOUT) might take place during the mentioned delay. As a consequence VOUT might not drop down enough to reset the host. The issue can be avoided by using open-drain instead of push-pull operation for such signals.

Interrupt output

A pin is set as an interrupt output by selecting INTHI or INTLO (active high or low, respectively) in the USAGE[n] register. The CONFIG[n] register is used to enable the output buffer and configure the settings.

GPIO can be used as an interrupt by setting one or more from the following registers: