The serial clock (SCK), often referred to as the serial bit clock, pulses once for each data bit being transferred on the serial data lines SDIN and SDOUT.
When operating in Master mode, the SCK is generated from the MCK, and the frequency of SCK is
then given as:
SCK = 2 * LRCK * CONFIG.SWIDTH The falling edge of the SCK falls on the toggling edge of LRCK.
When operating in Slave mode, SCK is provided by the external I2S master.