CONFIG.MCKEN

Address offset: 0x510

Master clock generator enable


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000001				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
ID	R/W	Field	Value ID	Value								Description
A	RW	MCKEN										Master clock generator enable
			Disabled	0								Master clock generator disabled and PSEL.MCK not connected(available as GPIO).
			Enabled	1								Master clock generator running and MCK output on PSEL.MCK.