The cyclic redundancy check (CRC) generator in RADIO calculates the CRC over the whole packet excluding the preamble.
The device also supports excluding the address field from the CRC calculation, see the CRCCNF.SKIPADDR register for more information.
The CRC polynomial is configurable as illustrated in the following figure, where bit 0 in the register CRCPOLY corresponds to X0 and bit n corresponds to Xn. See CRCPOLY for more information.
The figure shows that the CRC is calculated by feeding the packet serially through the CRC generator. Before the packet is clocked through the CRC generator, the CRC generator's latches b[0..n] will be initialized with a predefined value specified in the register CRCINIT. After the whole packet has been clocked through the CRC generator, b[0..n] will hold the resulting CRC. This value will be used by RADIO during both transmission and reception. The CPU cannont read latches b[0..n] at any time. However, a received CRC can be read by the CPU via the register RXCRC.
The length (n) of the CRC is configurable, see CRCCNF for more information.
When the entire packet including the CRC has been received, and no errors were detected, RADIO generates the event CRCOK. If CRC errors were detected, the event CRCERROR is generated.
The CRC check status can be read from the register CRCSTATUS after a packet has been received.