Address offset: 0xBC4
Buffered GPIO Output
Bits 15:0 in this register are passed to OUT on a Counter0 event (write sets dirty status). If external paramenter RT_SHIFT_PRESENT = 1, OUTB bit width is 32 and in addition to the described behavior, OUTB[31:16] is passed to OUTB[15:0] on a Counter0 event as well. Real Time Peripherals VIO
OUTB[15:0] shares a physical register with MINSTRET (lower 16 bits) and EVENTSB (lower 16 bits).
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | f | e | d | c | b | a | Z | Y | X | W | V | U | T | S | R | Q | P | O | N | M | L | K | J | I | H | G | F | E | D | C | B | A | |||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A-f |
RW |
PIN[i] (i=0..31) |
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|
LOW |
0x0 |
Pin driver is low |
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|
HIGH |
0x1 |
Pin driver is high |
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