The cache is a direct mapped cache. Both instruction and data accesses towards NVM memory are cached.
The cache has the following features:
- 4x64-bit cache line
- Ability to enable/disable cache at run-time
- Writes to cached memory are write-around and invalidate the cache line
- Manual invalidation
- Performance hit/miss counter registers for profiling CACHE operations
The cache must be enabled by the ENABLE register.