CPU and support module configuration

nRF54LS05B Datasheet

The Arm Cortex®-M33 processor has a number of CPU options and support modules implemented on the device.

Table 1. Core options
Option Description Implemented
WIC Wakeup Interrupt Controller No
Endianness Memory system endianness Little endian
DWT Data Watchpoint and Trace Yes
Table 2. Modules
Module Description Implemented
MPU Number of MPU regions 4
SAU Number of SAU regions 0
FPU Floating-point unit No
DSP Digital Signal Processing Extension No
Arm TrustZone® for Armv8-M Armv8-M Security Extensions No
CPIF Coprocessor interface No
ETM Embedded Trace Macrocell No
ITM Instrumentation Trace Macrocell No
MTB Micro Trace Buffer No
CTI Cross Trigger Interface No
BPU Breakpoint Unit Yes
INITVTOR Initial vector table offset 0x00000000