Instances
| Instance | Domain | Base address | Description |
|---|---|---|---|
| P1 | GLOBAL | 0x400D8200 |
General purpose input and output, port P1 |
| P0 | GLOBAL | 0x4010A000 |
General purpose input and output, port P0 |
Configuration
| Instance | Domain | Configuration |
|---|---|---|
| P1 | GLOBAL |
I/O pins on this port have pin sense mechanism This port has weak pull-ups on selected GPIO pins. P1 has 32 pins, P1.00 through P1.31. |
| P0 | GLOBAL |
I/O pins on this port have pin sense mechanism P0 has 5 pins, P0.00 through P0.04. |
Register overview
| Register | Offset | Description |
|---|---|---|
| OUT | 0x000 |
Write GPIO port This register is retained. |
| OUTSET | 0x004 |
Set individual bits in GPIO port |
| OUTCLR | 0x008 |
Clear individual bits in GPIO port |
| IN | 0x00C |
Read GPIO port |
| DIR | 0x010 |
Direction of GPIO pins This register is retained. |
| DIRSET | 0x014 |
DIR set register |
| DIRCLR | 0x018 |
DIR clear register |
| LATCH | 0x020 |
Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers This register is retained. |
| DETECTMODE | 0x024 |
Select between default DETECT signal behavior and LDETECT mode This register is retained. |
| PORTCNF.WEAKPU | 0x30 |
Control global weak pull-ups on the selected set of GPIO pins |
| PIN_CNF[n] | 0x080 |
Pin n configuration of GPIO pin This register is retained. |