To enable the RNG interrupt, enable the RNG field in the CRACEN.INTEN register and set the necessary INTEN bits in the CRACENCORE.RNGCONTROL.CONTROL register.
The RNG has two interrupt causes:
- FULLINT: set when the FIFO becomes full. It can be cleared when FIFO is no longer full by writing to the FIFOLEVEL register or activating soft-reset.
- ANYHEALTHTESTFAIL: set when an error is detected in any of the health tests. It is cleared when writing a zero to the corresponding bit in the status register or when the soft-reset is activated.
For each interrupt, there is a status bit in the STATUS register and an enable bit in the CONTROL register. The STATUS register state does not depend on the interrupt enable bits in the control register. The interrupt enable bits are only used to control the generation of the event CRACEN.EVENTS_RNG and the signal to the interrupt handler.