Registers

Instances


Instance	Domain	Base address	Description
SPIS20	GLOBAL	0x400C6000	SPI peripheral SPIS20
SPIS21	GLOBAL	0x400C7000	SPI peripheral SPIS21
SPIS22	GLOBAL	0x400C8000	SPI peripheral SPIS22

Configuration


Instance	Domain	Configuration
SPIS20	GLOBAL	Use GPIO port P1
SPIS21	GLOBAL	Use GPIO port P1
SPIS22	GLOBAL	Use GPIO port P1

Register overview


Register	Offset	Description
TASKS_ACQUIRE	0x014	Acquire SPI semaphore
TASKS_RELEASE	0x018	Release SPI semaphore, enabling the SPI slave to acquire it
TASKS_DMA.RX.ENABLEMATCH[n]	0x030	Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.
TASKS_DMA.RX.DISABLEMATCH[n]	0x040	Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.
SUBSCRIBE_ACQUIRE	0x094	Subscribe configuration for task ACQUIRE
SUBSCRIBE_RELEASE	0x098	Subscribe configuration for task RELEASE
SUBSCRIBE_DMA.RX.ENABLEMATCH[n]	0x0B0	Subscribe configuration for task ENABLEMATCH[n]
SUBSCRIBE_DMA.RX.DISABLEMATCH[n]	0x0C0	Subscribe configuration for task DISABLEMATCH[n]
EVENTS_END	0x104	Granted transaction completed
EVENTS_ACQUIRED	0x118	Semaphore acquired
EVENTS_DMA.RX.END	0x14C	Generated after all MAXCNT bytes have been transferred
EVENTS_DMA.RX.READY	0x150	Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.
EVENTS_DMA.RX.BUSERROR	0x154	An error occured during the bus transfer.
EVENTS_DMA.RX.MATCH[n]	0x158	Pattern match is detected on the DMA data bus.
EVENTS_DMA.TX.END	0x168	Generated after all MAXCNT bytes have been transferred
EVENTS_DMA.TX.READY	0x16C	Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.
EVENTS_DMA.TX.BUSERROR	0x170	An error occured during the bus transfer.
PUBLISH_END	0x184	Publish configuration for event END
PUBLISH_ACQUIRED	0x198	Publish configuration for event ACQUIRED
PUBLISH_DMA.RX.END	0x1CC	Publish configuration for event END
PUBLISH_DMA.RX.READY	0x1D0	Publish configuration for event READY
PUBLISH_DMA.RX.BUSERROR	0x1D4	Publish configuration for event BUSERROR
PUBLISH_DMA.RX.MATCH[n]	0x1D8	Publish configuration for event MATCH[n]
PUBLISH_DMA.TX.END	0x1E8	Publish configuration for event END
PUBLISH_DMA.TX.READY	0x1EC	Publish configuration for event READY
PUBLISH_DMA.TX.BUSERROR	0x1F0	Publish configuration for event BUSERROR
SHORTS	0x200	Shortcuts between local events and tasks
INTENSET	0x304	Enable interrupt
INTENCLR	0x308	Disable interrupt
SEMSTAT	0x400	Semaphore status register
STATUS	0x440	Status from last transaction
ENABLE	0x500	Enable SPI slave
CONFIG	0x554	Configuration register
DEF	0x55C	Default character. Character clocked out in case of an ignored transaction.
ORC	0x5C0	Over-read character
PSEL.SCK	0x600	Pin select for SCK
PSEL.MISO	0x604	Pin select for SDO signal
PSEL.MOSI	0x608	Pin select for SDI signal
PSEL.CSN	0x610	Pin select for CSN signal
DMA.RX.PTR	0x704	RAM buffer start address
DMA.RX.MAXCNT	0x708	Maximum number of bytes in channel buffer
DMA.RX.AMOUNT	0x70C	Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.
DMA.RX.TERMINATEONBUSERROR	0x71C	Terminate the transaction if a BUSERROR event is detected.
DMA.RX.BUSERRORADDRESS	0x720	Address of transaction that generated the last BUSERROR event.
DMA.RX.MATCH.CONFIG	0x724	Configure individual match events
DMA.RX.MATCH.CANDIDATE[n]	0x728	The data to look for - any match will trigger the MATCH[n] event, if enabled.
DMA.TX.PTR	0x73C	RAM buffer start address
DMA.TX.MAXCNT	0x740	Maximum number of bytes in channel buffer
DMA.TX.AMOUNT	0x744	Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.
DMA.TX.TERMINATEONBUSERROR	0x754	Terminate the transaction if a BUSERROR event is detected.
DMA.TX.BUSERRORADDRESS	0x758	Address of transaction that generated the last BUSERROR event.