Instances
| Instance | Domain | Base address | Description |
|---|---|---|---|
| GPIOTE20 | GLOBAL | 0x400DA000 |
8 channels and 1 interrupts for GPIO port P1 GPIO tasks and events GPIOTE20 |
| GPIOTE30 | GLOBAL | 0x4010C000 |
4 channels and 1 interrupts for GPIO port P0 GPIO tasks and events GPIOTE30 |
Configuration
| Instance | Domain | Configuration |
|---|---|---|
| GPIOTE20 | GLOBAL |
Number of GPIOTE channels: 0..7 Number of GPIOTE port events: 0..0 Number of GPIOTE interrupts: 0..0 |
| GPIOTE30 | GLOBAL |
Number of GPIOTE channels: 0..3 Number of GPIOTE port events: 0..0 Number of GPIOTE interrupts: 0..0 |
Register overview
| Register | Offset | Description |
|---|---|---|
| TASKS_OUT[n] | 0x000 |
Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. |
| TASKS_SET[n] | 0x030 |
Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. |
| TASKS_CLR[n] | 0x060 |
Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. |
| SUBSCRIBE_OUT[n] | 0x080 |
Subscribe configuration for task OUT[n] |
| SUBSCRIBE_SET[n] | 0x0B0 |
Subscribe configuration for task SET[n] |
| SUBSCRIBE_CLR[n] | 0x0E0 |
Subscribe configuration for task CLR[n] |
| EVENTS_IN[n] | 0x100 |
Event from pin specified in CONFIG[n].PSEL |
| EVENTS_PORT[n].NONSECURE | 0x140 |
Port event (the event name NONSECURE was chosen to be API compatible with devices that feature Arm TrustZone security) |
| PUBLISH_IN[n] | 0x180 |
Publish configuration for event IN[n] |
| PUBLISH_PORT[n].NONSECURE | 0x1C0 |
Publish configuration for event PORT[n].NONSECURE |
| INTENSET0 | 0x304 |
Enable interrupt |
| INTENCLR0 | 0x308 |
Disable interrupt |
| INTENSET1 | 0x314 |
Enable interrupt |
| INTENCLR1 | 0x318 |
Disable interrupt |
| CONFIG[n] | 0x510 |
Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event |