Sampling Process

When the output node of a high frequency ring oscillator (RO) is sampled at the rate of a low-frequency clock, then the sampled bit is random. The device ensures that T_osc >> T_RO, where T_osc is the duration during which the ring oscillator is free-running.

Two oscillation modes are supported: warm mode and cold mode.

In warm mode, the ring oscillators are free-running as long as the FIFO is being filled. Warm mode is selected by writing register COOLDOWNPERIOD = 0. A sample is taken every D_OSC clock cycles, where D_OSC is configured using the SAMPLINGPERIOD register. Note that the oscillation time T_OSC = D_OSC * T_CLK.

In cold mode, the ring oscillators are disabled for D_RST clock cycles after every sample. D_RST is configured through the COOLDOWNPERIOD register.

Note that in reality D_OSC is typically larger than what is suggested by the above figures, ensuring that T_OSC >> T_RST.

Warm mode could theoretically exhibit temporal correlations, unlike cold mode, which is rendered memoryless by resetting to a predefined state before each random data generation. To mitigate this in warm mode, an additional margin can be applied to T_OSC, by using the SAMPLINGPERIOD register. Health tests will activate if issues arise.

Cold mode may be more susceptible to side-channel attacks, as the cessation of oscillation offers a synchronization point, potentially allowing an attacker to more readily determine when samples are generated. Warm mode is not entirely immune to such vulnerabilities either, because the AES can produce a power signature that also serves as a synchronization point.

The warm mode will have a better throughput.

The choice between the two options depends on the application requirements. Both approaches are valid and pass the relevant test suites .